mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-30 21:29:28 +00:00
into their new header subdirectory: include/llvm/IR. This matches the directory structure of lib, and begins to correct a long standing point of file layout clutter in LLVM. There are still more header files to move here, but I wanted to handle them in separate commits to make tracking what files make sense at each layer easier. The only really questionable files here are the target intrinsic tablegen files. But that's a battle I'd rather not fight today. I've updated both CMake and Makefile build systems (I think, and my tests think, but I may have missed something). I've also re-sorted the includes throughout the project. I'll be committing updates to Clang, DragonEgg, and Polly momentarily. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171366 91177308-0d34-0410-b5e6-96231b3b80d8
560 lines
20 KiB
C++
560 lines
20 KiB
C++
//===-- SelectionDAGBuilder.h - Selection-DAG building --------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This implements routines for translating from LLVM IR into SelectionDAG IR.
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//
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//===----------------------------------------------------------------------===//
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#ifndef SELECTIONDAGBUILDER_H
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#define SELECTIONDAGBUILDER_H
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#include "llvm/ADT/APInt.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/SelectionDAGNodes.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/IR/Constants.h"
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#include "llvm/Support/CallSite.h"
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#include "llvm/Support/ErrorHandling.h"
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#include <vector>
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namespace llvm {
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class AliasAnalysis;
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class AllocaInst;
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class BasicBlock;
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class BitCastInst;
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class BranchInst;
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class CallInst;
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class DbgValueInst;
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class ExtractElementInst;
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class ExtractValueInst;
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class FCmpInst;
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class FPExtInst;
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class FPToSIInst;
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class FPToUIInst;
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class FPTruncInst;
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class Function;
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class FunctionLoweringInfo;
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class GetElementPtrInst;
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class GCFunctionInfo;
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class ICmpInst;
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class IntToPtrInst;
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class IndirectBrInst;
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class InvokeInst;
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class InsertElementInst;
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class InsertValueInst;
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class Instruction;
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class LoadInst;
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class MachineBasicBlock;
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class MachineInstr;
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class MachineRegisterInfo;
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class MDNode;
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class PHINode;
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class PtrToIntInst;
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class ReturnInst;
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class SDDbgValue;
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class SExtInst;
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class SelectInst;
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class ShuffleVectorInst;
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class SIToFPInst;
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class StoreInst;
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class SwitchInst;
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class DataLayout;
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class TargetLibraryInfo;
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class TargetLowering;
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class TruncInst;
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class UIToFPInst;
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class UnreachableInst;
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class VAArgInst;
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class ZExtInst;
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//===----------------------------------------------------------------------===//
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/// SelectionDAGBuilder - This is the common target-independent lowering
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/// implementation that is parameterized by a TargetLowering object.
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///
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class SelectionDAGBuilder {
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/// CurDebugLoc - current file + line number. Changes as we build the DAG.
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DebugLoc CurDebugLoc;
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DenseMap<const Value*, SDValue> NodeMap;
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/// UnusedArgNodeMap - Maps argument value for unused arguments. This is used
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/// to preserve debug information for incoming arguments.
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DenseMap<const Value*, SDValue> UnusedArgNodeMap;
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/// DanglingDebugInfo - Helper type for DanglingDebugInfoMap.
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class DanglingDebugInfo {
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const DbgValueInst* DI;
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DebugLoc dl;
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unsigned SDNodeOrder;
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public:
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DanglingDebugInfo() : DI(0), dl(DebugLoc()), SDNodeOrder(0) { }
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DanglingDebugInfo(const DbgValueInst *di, DebugLoc DL, unsigned SDNO) :
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DI(di), dl(DL), SDNodeOrder(SDNO) { }
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const DbgValueInst* getDI() { return DI; }
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DebugLoc getdl() { return dl; }
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unsigned getSDNodeOrder() { return SDNodeOrder; }
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};
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/// DanglingDebugInfoMap - Keeps track of dbg_values for which we have not
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/// yet seen the referent. We defer handling these until we do see it.
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DenseMap<const Value*, DanglingDebugInfo> DanglingDebugInfoMap;
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public:
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/// PendingLoads - Loads are not emitted to the program immediately. We bunch
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/// them up and then emit token factor nodes when possible. This allows us to
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/// get simple disambiguation between loads without worrying about alias
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/// analysis.
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SmallVector<SDValue, 8> PendingLoads;
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private:
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/// PendingExports - CopyToReg nodes that copy values to virtual registers
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/// for export to other blocks need to be emitted before any terminator
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/// instruction, but they have no other ordering requirements. We bunch them
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/// up and the emit a single tokenfactor for them just before terminator
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/// instructions.
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SmallVector<SDValue, 8> PendingExports;
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/// SDNodeOrder - A unique monotonically increasing number used to order the
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/// SDNodes we create.
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unsigned SDNodeOrder;
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/// Case - A struct to record the Value for a switch case, and the
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/// case's target basic block.
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struct Case {
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const Constant *Low;
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const Constant *High;
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MachineBasicBlock* BB;
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uint32_t ExtraWeight;
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Case() : Low(0), High(0), BB(0), ExtraWeight(0) { }
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Case(const Constant *low, const Constant *high, MachineBasicBlock *bb,
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uint32_t extraweight) : Low(low), High(high), BB(bb),
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ExtraWeight(extraweight) { }
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APInt size() const {
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const APInt &rHigh = cast<ConstantInt>(High)->getValue();
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const APInt &rLow = cast<ConstantInt>(Low)->getValue();
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return (rHigh - rLow + 1ULL);
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}
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};
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struct CaseBits {
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uint64_t Mask;
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MachineBasicBlock* BB;
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unsigned Bits;
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uint32_t ExtraWeight;
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CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits,
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uint32_t Weight):
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Mask(mask), BB(bb), Bits(bits), ExtraWeight(Weight) { }
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};
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typedef std::vector<Case> CaseVector;
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typedef std::vector<CaseBits> CaseBitsVector;
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typedef CaseVector::iterator CaseItr;
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typedef std::pair<CaseItr, CaseItr> CaseRange;
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/// CaseRec - A struct with ctor used in lowering switches to a binary tree
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/// of conditional branches.
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struct CaseRec {
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CaseRec(MachineBasicBlock *bb, const Constant *lt, const Constant *ge,
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CaseRange r) :
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CaseBB(bb), LT(lt), GE(ge), Range(r) {}
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/// CaseBB - The MBB in which to emit the compare and branch
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MachineBasicBlock *CaseBB;
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/// LT, GE - If nonzero, we know the current case value must be less-than or
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/// greater-than-or-equal-to these Constants.
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const Constant *LT;
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const Constant *GE;
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/// Range - A pair of iterators representing the range of case values to be
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/// processed at this point in the binary search tree.
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CaseRange Range;
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};
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typedef std::vector<CaseRec> CaseRecVector;
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struct CaseBitsCmp {
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bool operator()(const CaseBits &C1, const CaseBits &C2) {
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return C1.Bits > C2.Bits;
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}
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};
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size_t Clusterify(CaseVector &Cases, const SwitchInst &SI);
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/// CaseBlock - This structure is used to communicate between
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/// SelectionDAGBuilder and SDISel for the code generation of additional basic
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/// blocks needed by multi-case switch statements.
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struct CaseBlock {
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CaseBlock(ISD::CondCode cc, const Value *cmplhs, const Value *cmprhs,
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const Value *cmpmiddle,
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MachineBasicBlock *truebb, MachineBasicBlock *falsebb,
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MachineBasicBlock *me,
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uint32_t trueweight = 0, uint32_t falseweight = 0)
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: CC(cc), CmpLHS(cmplhs), CmpMHS(cmpmiddle), CmpRHS(cmprhs),
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TrueBB(truebb), FalseBB(falsebb), ThisBB(me),
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TrueWeight(trueweight), FalseWeight(falseweight) { }
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// CC - the condition code to use for the case block's setcc node
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ISD::CondCode CC;
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// CmpLHS/CmpRHS/CmpMHS - The LHS/MHS/RHS of the comparison to emit.
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// Emit by default LHS op RHS. MHS is used for range comparisons:
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// If MHS is not null: (LHS <= MHS) and (MHS <= RHS).
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const Value *CmpLHS, *CmpMHS, *CmpRHS;
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// TrueBB/FalseBB - the block to branch to if the setcc is true/false.
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MachineBasicBlock *TrueBB, *FalseBB;
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// ThisBB - the block into which to emit the code for the setcc and branches
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MachineBasicBlock *ThisBB;
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// TrueWeight/FalseWeight - branch weights.
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uint32_t TrueWeight, FalseWeight;
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};
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struct JumpTable {
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JumpTable(unsigned R, unsigned J, MachineBasicBlock *M,
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MachineBasicBlock *D): Reg(R), JTI(J), MBB(M), Default(D) {}
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/// Reg - the virtual register containing the index of the jump table entry
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//. to jump to.
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unsigned Reg;
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/// JTI - the JumpTableIndex for this jump table in the function.
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unsigned JTI;
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/// MBB - the MBB into which to emit the code for the indirect jump.
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MachineBasicBlock *MBB;
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/// Default - the MBB of the default bb, which is a successor of the range
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/// check MBB. This is when updating PHI nodes in successors.
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MachineBasicBlock *Default;
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};
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struct JumpTableHeader {
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JumpTableHeader(APInt F, APInt L, const Value *SV, MachineBasicBlock *H,
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bool E = false):
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First(F), Last(L), SValue(SV), HeaderBB(H), Emitted(E) {}
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APInt First;
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APInt Last;
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const Value *SValue;
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MachineBasicBlock *HeaderBB;
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bool Emitted;
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};
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typedef std::pair<JumpTableHeader, JumpTable> JumpTableBlock;
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struct BitTestCase {
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BitTestCase(uint64_t M, MachineBasicBlock* T, MachineBasicBlock* Tr,
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uint32_t Weight):
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Mask(M), ThisBB(T), TargetBB(Tr), ExtraWeight(Weight) { }
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uint64_t Mask;
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MachineBasicBlock *ThisBB;
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MachineBasicBlock *TargetBB;
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uint32_t ExtraWeight;
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};
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typedef SmallVector<BitTestCase, 3> BitTestInfo;
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struct BitTestBlock {
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BitTestBlock(APInt F, APInt R, const Value* SV,
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unsigned Rg, MVT RgVT, bool E,
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MachineBasicBlock* P, MachineBasicBlock* D,
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const BitTestInfo& C):
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First(F), Range(R), SValue(SV), Reg(Rg), RegVT(RgVT), Emitted(E),
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Parent(P), Default(D), Cases(C) { }
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APInt First;
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APInt Range;
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const Value *SValue;
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unsigned Reg;
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MVT RegVT;
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bool Emitted;
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MachineBasicBlock *Parent;
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MachineBasicBlock *Default;
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BitTestInfo Cases;
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};
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public:
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// TLI - This is information that describes the available target features we
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// need for lowering. This indicates when operations are unavailable,
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// implemented with a libcall, etc.
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const TargetMachine &TM;
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const TargetLowering &TLI;
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SelectionDAG &DAG;
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const DataLayout *TD;
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AliasAnalysis *AA;
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const TargetLibraryInfo *LibInfo;
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/// SwitchCases - Vector of CaseBlock structures used to communicate
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/// SwitchInst code generation information.
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std::vector<CaseBlock> SwitchCases;
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/// JTCases - Vector of JumpTable structures used to communicate
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/// SwitchInst code generation information.
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std::vector<JumpTableBlock> JTCases;
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/// BitTestCases - Vector of BitTestBlock structures used to communicate
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/// SwitchInst code generation information.
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std::vector<BitTestBlock> BitTestCases;
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// Emit PHI-node-operand constants only once even if used by multiple
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// PHI nodes.
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DenseMap<const Constant *, unsigned> ConstantsOut;
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/// FuncInfo - Information about the function as a whole.
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///
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FunctionLoweringInfo &FuncInfo;
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/// OptLevel - What optimization level we're generating code for.
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///
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CodeGenOpt::Level OptLevel;
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/// GFI - Garbage collection metadata for the function.
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GCFunctionInfo *GFI;
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/// LPadToCallSiteMap - Map a landing pad to the call site indexes.
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DenseMap<MachineBasicBlock*, SmallVector<unsigned, 4> > LPadToCallSiteMap;
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/// HasTailCall - This is set to true if a call in the current
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/// block has been translated as a tail call. In this case,
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/// no subsequent DAG nodes should be created.
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///
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bool HasTailCall;
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LLVMContext *Context;
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SelectionDAGBuilder(SelectionDAG &dag, FunctionLoweringInfo &funcinfo,
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CodeGenOpt::Level ol)
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: SDNodeOrder(0), TM(dag.getTarget()), TLI(dag.getTargetLoweringInfo()),
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DAG(dag), FuncInfo(funcinfo), OptLevel(ol),
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HasTailCall(false) {
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}
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void init(GCFunctionInfo *gfi, AliasAnalysis &aa,
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const TargetLibraryInfo *li);
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/// clear - Clear out the current SelectionDAG and the associated
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/// state and prepare this SelectionDAGBuilder object to be used
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/// for a new block. This doesn't clear out information about
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/// additional blocks that are needed to complete switch lowering
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/// or PHI node updating; that information is cleared out as it is
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/// consumed.
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void clear();
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/// clearDanglingDebugInfo - Clear the dangling debug information
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/// map. This function is separated from the clear so that debug
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/// information that is dangling in a basic block can be properly
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/// resolved in a different basic block. This allows the
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/// SelectionDAG to resolve dangling debug information attached
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/// to PHI nodes.
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void clearDanglingDebugInfo();
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/// getRoot - Return the current virtual root of the Selection DAG,
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/// flushing any PendingLoad items. This must be done before emitting
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/// a store or any other node that may need to be ordered after any
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/// prior load instructions.
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///
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SDValue getRoot();
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/// getControlRoot - Similar to getRoot, but instead of flushing all the
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/// PendingLoad items, flush all the PendingExports items. It is necessary
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/// to do this before emitting a terminator instruction.
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///
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SDValue getControlRoot();
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DebugLoc getCurDebugLoc() const { return CurDebugLoc; }
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unsigned getSDNodeOrder() const { return SDNodeOrder; }
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void CopyValueToVirtualRegister(const Value *V, unsigned Reg);
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/// AssignOrderingToNode - Assign an ordering to the node. The order is gotten
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/// from how the code appeared in the source. The ordering is used by the
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/// scheduler to effectively turn off scheduling.
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void AssignOrderingToNode(const SDNode *Node);
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void visit(const Instruction &I);
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void visit(unsigned Opcode, const User &I);
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// resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
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// generate the debug data structures now that we've seen its definition.
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void resolveDanglingDebugInfo(const Value *V, SDValue Val);
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SDValue getValue(const Value *V);
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SDValue getNonRegisterValue(const Value *V);
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SDValue getValueImpl(const Value *V);
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void setValue(const Value *V, SDValue NewN) {
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SDValue &N = NodeMap[V];
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assert(N.getNode() == 0 && "Already set a value for this node!");
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N = NewN;
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}
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void setUnusedArgValue(const Value *V, SDValue NewN) {
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SDValue &N = UnusedArgNodeMap[V];
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assert(N.getNode() == 0 && "Already set a value for this node!");
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N = NewN;
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}
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void FindMergedConditions(const Value *Cond, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB, MachineBasicBlock *CurBB,
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MachineBasicBlock *SwitchBB, unsigned Opc);
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void EmitBranchForMergedCondition(const Value *Cond, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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MachineBasicBlock *CurBB,
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MachineBasicBlock *SwitchBB);
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bool ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases);
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bool isExportableFromCurrentBlock(const Value *V, const BasicBlock *FromBB);
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void CopyToExportRegsIfNeeded(const Value *V);
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void ExportFromCurrentBlock(const Value *V);
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void LowerCallTo(ImmutableCallSite CS, SDValue Callee, bool IsTailCall,
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MachineBasicBlock *LandingPad = NULL);
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/// UpdateSplitBlock - When an MBB was split during scheduling, update the
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/// references that ned to refer to the last resulting block.
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void UpdateSplitBlock(MachineBasicBlock *First, MachineBasicBlock *Last);
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private:
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// Terminator instructions.
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void visitRet(const ReturnInst &I);
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void visitBr(const BranchInst &I);
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void visitSwitch(const SwitchInst &I);
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void visitIndirectBr(const IndirectBrInst &I);
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void visitUnreachable(const UnreachableInst &I) { /* noop */ }
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// Helpers for visitSwitch
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bool handleSmallSwitchRange(CaseRec& CR,
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CaseRecVector& WorkList,
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const Value* SV,
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MachineBasicBlock* Default,
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MachineBasicBlock *SwitchBB);
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bool handleJTSwitchCase(CaseRec& CR,
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CaseRecVector& WorkList,
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const Value* SV,
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MachineBasicBlock* Default,
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MachineBasicBlock *SwitchBB);
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bool handleBTSplitSwitchCase(CaseRec& CR,
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CaseRecVector& WorkList,
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const Value* SV,
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MachineBasicBlock* Default,
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MachineBasicBlock *SwitchBB);
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bool handleBitTestsSwitchCase(CaseRec& CR,
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CaseRecVector& WorkList,
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const Value* SV,
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MachineBasicBlock* Default,
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MachineBasicBlock *SwitchBB);
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uint32_t getEdgeWeight(const MachineBasicBlock *Src,
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const MachineBasicBlock *Dst) const;
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void addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst,
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uint32_t Weight = 0);
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public:
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void visitSwitchCase(CaseBlock &CB,
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MachineBasicBlock *SwitchBB);
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void visitBitTestHeader(BitTestBlock &B, MachineBasicBlock *SwitchBB);
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void visitBitTestCase(BitTestBlock &BB,
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MachineBasicBlock* NextMBB,
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uint32_t BranchWeightToNext,
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unsigned Reg,
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BitTestCase &B,
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MachineBasicBlock *SwitchBB);
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void visitJumpTable(JumpTable &JT);
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void visitJumpTableHeader(JumpTable &JT, JumpTableHeader &JTH,
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MachineBasicBlock *SwitchBB);
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private:
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// These all get lowered before this pass.
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void visitInvoke(const InvokeInst &I);
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void visitResume(const ResumeInst &I);
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void visitBinary(const User &I, unsigned OpCode);
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void visitShift(const User &I, unsigned Opcode);
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void visitAdd(const User &I) { visitBinary(I, ISD::ADD); }
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void visitFAdd(const User &I) { visitBinary(I, ISD::FADD); }
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void visitSub(const User &I) { visitBinary(I, ISD::SUB); }
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void visitFSub(const User &I);
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void visitMul(const User &I) { visitBinary(I, ISD::MUL); }
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void visitFMul(const User &I) { visitBinary(I, ISD::FMUL); }
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void visitURem(const User &I) { visitBinary(I, ISD::UREM); }
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void visitSRem(const User &I) { visitBinary(I, ISD::SREM); }
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void visitFRem(const User &I) { visitBinary(I, ISD::FREM); }
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void visitUDiv(const User &I) { visitBinary(I, ISD::UDIV); }
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|
void visitSDiv(const User &I);
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void visitFDiv(const User &I) { visitBinary(I, ISD::FDIV); }
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void visitAnd (const User &I) { visitBinary(I, ISD::AND); }
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void visitOr (const User &I) { visitBinary(I, ISD::OR); }
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void visitXor (const User &I) { visitBinary(I, ISD::XOR); }
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void visitShl (const User &I) { visitShift(I, ISD::SHL); }
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void visitLShr(const User &I) { visitShift(I, ISD::SRL); }
|
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void visitAShr(const User &I) { visitShift(I, ISD::SRA); }
|
|
void visitICmp(const User &I);
|
|
void visitFCmp(const User &I);
|
|
// Visit the conversion instructions
|
|
void visitTrunc(const User &I);
|
|
void visitZExt(const User &I);
|
|
void visitSExt(const User &I);
|
|
void visitFPTrunc(const User &I);
|
|
void visitFPExt(const User &I);
|
|
void visitFPToUI(const User &I);
|
|
void visitFPToSI(const User &I);
|
|
void visitUIToFP(const User &I);
|
|
void visitSIToFP(const User &I);
|
|
void visitPtrToInt(const User &I);
|
|
void visitIntToPtr(const User &I);
|
|
void visitBitCast(const User &I);
|
|
|
|
void visitExtractElement(const User &I);
|
|
void visitInsertElement(const User &I);
|
|
void visitShuffleVector(const User &I);
|
|
|
|
void visitExtractValue(const ExtractValueInst &I);
|
|
void visitInsertValue(const InsertValueInst &I);
|
|
void visitLandingPad(const LandingPadInst &I);
|
|
|
|
void visitGetElementPtr(const User &I);
|
|
void visitSelect(const User &I);
|
|
|
|
void visitAlloca(const AllocaInst &I);
|
|
void visitLoad(const LoadInst &I);
|
|
void visitStore(const StoreInst &I);
|
|
void visitAtomicCmpXchg(const AtomicCmpXchgInst &I);
|
|
void visitAtomicRMW(const AtomicRMWInst &I);
|
|
void visitFence(const FenceInst &I);
|
|
void visitPHI(const PHINode &I);
|
|
void visitCall(const CallInst &I);
|
|
bool visitMemCmpCall(const CallInst &I);
|
|
bool visitUnaryFloatCall(const CallInst &I, unsigned Opcode);
|
|
void visitAtomicLoad(const LoadInst &I);
|
|
void visitAtomicStore(const StoreInst &I);
|
|
|
|
void visitInlineAsm(ImmutableCallSite CS);
|
|
const char *visitIntrinsicCall(const CallInst &I, unsigned Intrinsic);
|
|
void visitTargetIntrinsic(const CallInst &I, unsigned Intrinsic);
|
|
|
|
void visitVAStart(const CallInst &I);
|
|
void visitVAArg(const VAArgInst &I);
|
|
void visitVAEnd(const CallInst &I);
|
|
void visitVACopy(const CallInst &I);
|
|
|
|
void visitUserOp1(const Instruction &I) {
|
|
llvm_unreachable("UserOp1 should not exist at instruction selection time!");
|
|
}
|
|
void visitUserOp2(const Instruction &I) {
|
|
llvm_unreachable("UserOp2 should not exist at instruction selection time!");
|
|
}
|
|
|
|
void HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB);
|
|
|
|
/// EmitFuncArgumentDbgValue - If V is an function argument then create
|
|
/// corresponding DBG_VALUE machine instruction for it now. At the end of
|
|
/// instruction selection, they will be inserted to the entry BB.
|
|
bool EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable,
|
|
int64_t Offset, const SDValue &N);
|
|
};
|
|
|
|
} // end namespace llvm
|
|
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|
#endif
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