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b6cbecd272
When VSX is available, these instructions should be used in preference to the older variants that only have access to the scalar floating-point registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204559 91177308-0d34-0410-b5e6-96231b3b80d8
108 lines
2.5 KiB
LLVM
108 lines
2.5 KiB
LLVM
; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=g5 | FileCheck %s
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; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr6 | FileCheck -check-prefix=CHECK-PWR6 %s
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; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 | FileCheck -check-prefix=CHECK-A2 %s
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; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=+vsx | FileCheck -check-prefix=CHECK-VSX %s
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target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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define float @foo(i32 %a) nounwind {
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entry:
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%x = sitofp i32 %a to float
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ret float %x
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; CHECK: @foo
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; CHECK: extsw [[REG:[0-9]+]], 3
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; CHECK: std [[REG]],
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; CHECK: lfd [[REG2:[0-9]+]],
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; CHECK: fcfid [[REG3:[0-9]+]], [[REG2]]
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; CHECK: frsp 1, [[REG3]]
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; CHECK: blr
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; CHECK-PWR6: @foo
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; CHECK-PWR6: stw 3,
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; CHECK-PWR6: lfiwax [[REG:[0-9]+]],
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; CHECK-PWR6: fcfid [[REG2:[0-9]+]], [[REG]]
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; CHECK-PWR6: frsp 1, [[REG2]]
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; CHECK-PWR6: blr
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; CHECK-A2: @foo
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; CHECK-A2: stw 3,
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; CHECK-A2: lfiwax [[REG:[0-9]+]],
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; CHECK-A2: fcfids 1, [[REG]]
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; CHECK-A2: blr
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; CHECK-VSX: @foo
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; CHECK-VSX: stw 3,
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; CHECK-VSX: lfiwax [[REG:[0-9]+]],
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; CHECK-VSX: fcfids 1, [[REG]]
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; CHECK-VSX: blr
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}
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define double @goo(i32 %a) nounwind {
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entry:
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%x = sitofp i32 %a to double
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ret double %x
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; CHECK: @goo
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; CHECK: extsw [[REG:[0-9]+]], 3
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; CHECK: std [[REG]],
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; CHECK: lfd [[REG2:[0-9]+]],
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; CHECK: fcfid 1, [[REG2]]
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; CHECK: blr
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; CHECK-PWR6: @goo
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; CHECK-PWR6: stw 3,
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; CHECK-PWR6: lfiwax [[REG:[0-9]+]],
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; CHECK-PWR6: fcfid 1, [[REG]]
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; CHECK-PWR6: blr
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; CHECK-A2: @goo
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; CHECK-A2: stw 3,
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; CHECK-A2: lfiwax [[REG:[0-9]+]],
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; CHECK-A2: fcfid 1, [[REG]]
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; CHECK-A2: blr
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; CHECK-VSX: @goo
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; CHECK-VSX: stw 3,
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; CHECK-VSX: lfiwax [[REG:[0-9]+]],
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; CHECK-VSX: xscvsxddp 1, [[REG]]
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; CHECK-VSX: blr
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}
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define float @foou(i32 %a) nounwind {
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entry:
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%x = uitofp i32 %a to float
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ret float %x
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; CHECK-A2: @foou
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; CHECK-A2: stw 3,
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; CHECK-A2: lfiwzx [[REG:[0-9]+]],
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; CHECK-A2: fcfidus 1, [[REG]]
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; CHECK-A2: blr
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; CHECK-VSX: @foou
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; CHECK-VSX: stw 3,
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; CHECK-VSX: lfiwzx [[REG:[0-9]+]],
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; CHECK-VSX: fcfidus 1, [[REG]]
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; CHECK-VSX: blr
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}
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define double @goou(i32 %a) nounwind {
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entry:
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%x = uitofp i32 %a to double
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ret double %x
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; CHECK-A2: @goou
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; CHECK-A2: stw 3,
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; CHECK-A2: lfiwzx [[REG:[0-9]+]],
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; CHECK-A2: fcfidu 1, [[REG]]
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; CHECK-A2: blr
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; CHECK-VSX: @goou
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; CHECK-VSX: stw 3,
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; CHECK-VSX: lfiwzx [[REG:[0-9]+]],
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; CHECK-VSX: xscvuxddp 1, [[REG]]
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; CHECK-VSX: blr
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}
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