llvm-6502/test/CodeGen/PowerPC/quadint-return.ll
David Blaikie 7c9c6ed761 [opaque pointer type] Add textual IR support for explicit type parameter to load instruction
Essentially the same as the GEP change in r230786.

A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)

import fileinput
import sys
import re

pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")

for line in sys.stdin:
  sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))

Reviewers: rafael, dexonsmith, grosser

Differential Revision: http://reviews.llvm.org/D7649

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-27 21:17:42 +00:00

20 lines
583 B
LLVM

; REQUIRES: asserts
; RUN: llc -O0 -debug -o - < %s 2>&1 | FileCheck %s
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu"
define i128 @foo() nounwind {
entry:
%x = alloca i128, align 16
store i128 27, i128* %x, align 16
%0 = load i128, i128* %x, align 16
ret i128 %0
}
; CHECK: ********** Function: foo
; CHECK: ********** FAST REGISTER ALLOCATION **********
; CHECK: %X3<def> = COPY %vreg
; CHECK-NEXT: %X4<def> = COPY %vreg
; CHECK-NEXT: BLR