llvm-6502/test/CodeGen/SystemZ/int-cmp-41.ll
David Blaikie 7c9c6ed761 [opaque pointer type] Add textual IR support for explicit type parameter to load instruction
Essentially the same as the GEP change in r230786.

A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)

import fileinput
import sys
import re

pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")

for line in sys.stdin:
  sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))

Reviewers: rafael, dexonsmith, grosser

Differential Revision: http://reviews.llvm.org/D7649

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-27 21:17:42 +00:00

122 lines
2.7 KiB
LLVM

; Test 64-bit comparisons in which the second operand is sign-extended
; from a PC-relative i32.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
@g = global i32 1
@h = global i32 1, align 2, section "foo"
; Check signed comparison.
define i64 @f1(i64 %src1) {
; CHECK-LABEL: f1:
; CHECK: cgfrl %r2, g
; CHECK-NEXT: jl
; CHECK: br %r14
entry:
%val = load i32 , i32 *@g
%src2 = sext i32 %val to i64
%cond = icmp slt i64 %src1, %src2
br i1 %cond, label %exit, label %mulb
mulb:
%mul = mul i64 %src1, %src1
br label %exit
exit:
%res = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
ret i64 %res
}
; Check unsigned comparison, which cannot use CHRL.
define i64 @f2(i64 %src1) {
; CHECK-LABEL: f2:
; CHECK-NOT: cgfrl
; CHECK: br %r14
entry:
%val = load i32 , i32 *@g
%src2 = sext i32 %val to i64
%cond = icmp ult i64 %src1, %src2
br i1 %cond, label %exit, label %mulb
mulb:
%mul = mul i64 %src1, %src1
br label %exit
exit:
%res = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
ret i64 %res
}
; Check equality.
define i64 @f3(i64 %src1) {
; CHECK-LABEL: f3:
; CHECK: cgfrl %r2, g
; CHECK-NEXT: je
; CHECK: br %r14
entry:
%val = load i32 , i32 *@g
%src2 = sext i32 %val to i64
%cond = icmp eq i64 %src1, %src2
br i1 %cond, label %exit, label %mulb
mulb:
%mul = mul i64 %src1, %src1
br label %exit
exit:
%res = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
ret i64 %res
}
; Check inequality.
define i64 @f4(i64 %src1) {
; CHECK-LABEL: f4:
; CHECK: cgfrl %r2, g
; CHECK-NEXT: jlh
; CHECK: br %r14
entry:
%val = load i32 , i32 *@g
%src2 = sext i32 %val to i64
%cond = icmp ne i64 %src1, %src2
br i1 %cond, label %exit, label %mulb
mulb:
%mul = mul i64 %src1, %src1
br label %exit
exit:
%res = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
ret i64 %res
}
; Repeat f1 with an unaligned address.
define i64 @f5(i64 %src1) {
; CHECK-LABEL: f5:
; CHECK: larl [[REG:%r[0-5]]], h
; CHECK: cgf %r2, 0([[REG]])
; CHECK-NEXT: jl
; CHECK: br %r14
entry:
%val = load i32 , i32 *@h, align 2
%src2 = sext i32 %val to i64
%cond = icmp slt i64 %src1, %src2
br i1 %cond, label %exit, label %mulb
mulb:
%mul = mul i64 %src1, %src1
br label %exit
exit:
%res = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
ret i64 %res
}
; Check the comparison can be reversed if that allows CGFRL to be used.
define i64 @f6(i64 %src2) {
; CHECK-LABEL: f6:
; CHECK: cgfrl %r2, g
; CHECK-NEXT: jh {{\.L.*}}
; CHECK: br %r14
entry:
%val = load i32 , i32 *@g
%src1 = sext i32 %val to i64
%cond = icmp slt i64 %src1, %src2
br i1 %cond, label %exit, label %mulb
mulb:
%mul = mul i64 %src2, %src2
br label %exit
exit:
%res = phi i64 [ %src2, %entry ], [ %mul, %mulb ]
ret i64 %res
}