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https://github.com/c64scene-ar/llvm-6502.git
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b83bf52113
I've no idea why I decided to handle TMxx differently from all the other high/low logic operations, but it was a stupid thing to do. The high registers aren't available as separate 32-bit registers on z10, so subreg_h32 can't be used on a GR64 there. I've normally been testing with z196 and with -O3 and so hadn't noticed this until now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195473 91177308-0d34-0410-b5e6-96231b3b80d8
50 lines
944 B
LLVM
50 lines
944 B
LLVM
; That that we don't try to use z196 instructions on z10 for TMHH and TMHL.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 -O0 | FileCheck %s
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@g = global i32 0
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; Check the lowest useful TMHL value.
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define void @f1(i64 %a) {
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; CHECK-LABEL: f1:
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; CHECK-NOT: risblg
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; CHECK-NOT: risbhg
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; CHECK: tmhl {{%r[0-5]}}, 1
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; CHECK-NOT: risblg
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; CHECK-NOT: risbhg
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; CHECK: br %r14
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entry:
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%and = and i64 %a, 4294967296
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%cmp = icmp eq i64 %and, 0
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br i1 %cmp, label %exit, label %store
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store:
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store i32 1, i32 *@g
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br label %exit
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exit:
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ret void
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}
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; Check the lowest useful TMHH value.
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define void @f2(i64 %a) {
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; CHECK-LABEL: f2:
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; CHECK-NOT: risblg
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; CHECK-NOT: risbhg
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; CHECK: tmhh {{%r[0-5]}}, 1
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; CHECK-NOT: risblg
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; CHECK-NOT: risbhg
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; CHECK: br %r14
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entry:
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%and = and i64 %a, 281474976710656
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%cmp = icmp ne i64 %and, 0
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br i1 %cmp, label %exit, label %store
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store:
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store i32 1, i32 *@g
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br label %exit
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exit:
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ret void
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}
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