mirror of
https://github.com/c64scene-ar/llvm-6502.git
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db5c1f3d76
The zext handling added in r197802 wasn't right for RNSBG. This patch restricts it to ROSBG, RXSBG and RISBG. (The tests for RISBG were added in r197802 since RISBG was the motivating example.) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198862 91177308-0d34-0410-b5e6-96231b3b80d8
122 lines
2.5 KiB
LLVM
122 lines
2.5 KiB
LLVM
; Test sequences that can use ROSBG.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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; Test the simple case.
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define i32 @f1(i32 %a, i32 %b) {
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; CHECK-LABEL: f1:
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; CHECK: rosbg %r2, %r3, 59, 59, 0
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; CHECK: br %r14
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%andb = and i32 %b, 16
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%or = or i32 %a, %andb
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ret i32 %or
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}
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; ...and again with i64.
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define i64 @f2(i64 %a, i64 %b) {
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; CHECK-LABEL: f2:
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; CHECK: rosbg %r2, %r3, 59, 59, 0
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; CHECK: br %r14
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%andb = and i64 %b, 16
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%or = or i64 %a, %andb
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ret i64 %or
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}
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; Test a case where wraparound is needed.
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define i32 @f3(i32 %a, i32 %b) {
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; CHECK-LABEL: f3:
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; CHECK: rosbg %r2, %r3, 63, 60, 0
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; CHECK: br %r14
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%andb = and i32 %b, -7
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%or = or i32 %a, %andb
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ret i32 %or
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}
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; ...and again with i64.
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define i64 @f4(i64 %a, i64 %b) {
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; CHECK-LABEL: f4:
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; CHECK: rosbg %r2, %r3, 63, 60, 0
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; CHECK: br %r14
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%andb = and i64 %b, -7
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%or = or i64 %a, %andb
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ret i64 %or
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}
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; Test a case with just a shift.
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define i32 @f6(i32 %a, i32 %b) {
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; CHECK-LABEL: f6:
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; CHECK: rosbg %r2, %r3, 32, 51, 12
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; CHECK: br %r14
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%shrb = shl i32 %b, 12
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%or = or i32 %a, %shrb
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ret i32 %or
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}
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; ...and again with i64.
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define i64 @f7(i64 %a, i64 %b) {
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; CHECK-LABEL: f7:
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; CHECK: rosbg %r2, %r3, 0, 51, 12
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; CHECK: br %r14
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%shrb = shl i64 %b, 12
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%or = or i64 %a, %shrb
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ret i64 %or
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}
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; Test a case with just a rotate. This can't use ROSBG.
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define i32 @f8(i32 %a, i32 %b) {
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; CHECK-LABEL: f8:
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; CHECK: rll {{%r[0-5]}}
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; CHECK: or {{%r[0-5]}}
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; CHECK: br %r14
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%shlb = shl i32 %b, 30
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%shrb = lshr i32 %b, 2
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%rotlb = or i32 %shlb, %shrb
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%or = or i32 %a, %rotlb
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ret i32 %or
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}
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; ...and again with i64, which can.
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define i64 @f9(i64 %a, i64 %b) {
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; CHECK-LABEL: f9:
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; CHECK: rosbg %r2, %r3, 0, 63, 47
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; CHECK: br %r14
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%shlb = shl i64 %b, 47
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%shrb = lshr i64 %b, 17
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%rotlb = or i64 %shlb, %shrb
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%or = or i64 %a, %rotlb
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ret i64 %or
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}
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; Test a case with a shift and AND.
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define i32 @f10(i32 %a, i32 %b) {
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; CHECK-LABEL: f10:
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; CHECK: rosbg %r2, %r3, 56, 59, 4
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; CHECK: br %r14
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%shrb = shl i32 %b, 4
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%andb = and i32 %shrb, 240
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%or = or i32 %a, %andb
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ret i32 %or
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}
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; ...and again with i64.
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define i64 @f11(i64 %a, i64 %b) {
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; CHECK-LABEL: f11:
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; CHECK: rosbg %r2, %r3, 56, 59, 4
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; CHECK: br %r14
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%shrb = shl i64 %b, 4
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%andb = and i64 %shrb, 240
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%or = or i64 %a, %andb
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ret i64 %or
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}
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; Check the handling of zext and OR, which can use ROSBG.
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define i64 @f12(i64 %a, i32 %b) {
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; CHECK-LABEL: f12:
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; CHECK: rosbg %r2, %r3, 32, 63, 0
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; CHECK: br %r14
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%add = add i32 %b, 1
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%ext = zext i32 %add to i64
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%or = or i64 %a, %ext
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ret i64 %or
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}
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