llvm-6502/test/CodeGen/X86/2009-07-20-DAGCombineBug.ll
David Blaikie 7c9c6ed761 [opaque pointer type] Add textual IR support for explicit type parameter to load instruction
Essentially the same as the GEP change in r230786.

A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)

import fileinput
import sys
import re

pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")

for line in sys.stdin:
  sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))

Reviewers: rafael, dexonsmith, grosser

Differential Revision: http://reviews.llvm.org/D7649

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-27 21:17:42 +00:00

30 lines
822 B
LLVM

; RUN: llc < %s -march=x86
@bsBuff = internal global i32 0 ; <i32*> [#uses=1]
@llvm.used = appending global [1 x i8*] [i8* bitcast (i32 ()* @bsGetUInt32 to i8*)], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0]
define fastcc i32 @bsGetUInt32() nounwind ssp {
entry:
%bsBuff.promoted44 = load i32, i32* @bsBuff ; <i32> [#uses=1]
%0 = add i32 0, -8 ; <i32> [#uses=1]
%1 = lshr i32 %bsBuff.promoted44, %0 ; <i32> [#uses=1]
%2 = shl i32 %1, 8 ; <i32> [#uses=1]
br label %bb3.i17
bb3.i9: ; preds = %bb3.i17
br i1 false, label %bb2.i16, label %bb1.i15
bb1.i15: ; preds = %bb3.i9
unreachable
bb2.i16: ; preds = %bb3.i9
br label %bb3.i17
bb3.i17: ; preds = %bb2.i16, %entry
br i1 false, label %bb3.i9, label %bsR.exit18
bsR.exit18: ; preds = %bb3.i17
%3 = or i32 0, %2 ; <i32> [#uses=0]
ret i32 0
}