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https://github.com/c64scene-ar/llvm-6502.git
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b2f47c6a34
ConstantSDNodes (or UNDEFs) into a simple BUILD_VECTOR. For example, given the following sequence of dag nodes: i32 C = Constant<1> v4i32 V = BUILD_VECTOR C, C, C, C v4i32 Result = SIGN_EXTEND_INREG V, ValueType:v4i1 The SIGN_EXTEND_INREG node can be folded into a build_vector since the vector in input is a BUILD_VECTOR of constants. The optimized sequence is: i32 C = Constant<-1> v4i32 Result = BUILD_VECTOR C, C, C, C git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198084 91177308-0d34-0410-b5e6-96231b3b80d8
30 lines
1.3 KiB
LLVM
30 lines
1.3 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7 | FileCheck %s
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; ModuleID = '<stdin>'
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
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target triple = "x86_64-apple-darwin11.2.0"
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; During legalization, the vselect mask is 'type legalized' into a
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; wider BUILD_VECTOR. This causes the introduction of a new
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; sign_extend_inreg in the DAG.
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;
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; A sign_extend_inreg of a vector of ConstantSDNode or undef can be
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; always folded into a simple build_vector.
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;
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; Make sure that the sign_extend_inreg is simplified and that we
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; don't generate psll, psraw and pblendvb from the vselect.
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; CHECK-LABEL: foo8
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; CHECK-NOT: psll
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; CHECK-NOT: psraw
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; CHECK-NOT: pblendvb
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; CHECK: ret
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define void @foo8(float* nocapture %RET) nounwind {
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allocas:
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%resultvec.i = select <8 x i1> <i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true>, <8 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, <8 x i8> <i8 100, i8 100, i8 100, i8 100, i8 100, i8 100, i8 100, i8 100>
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%uint2float = uitofp <8 x i8> %resultvec.i to <8 x float>
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%ptr = bitcast float * %RET to <8 x float> *
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store <8 x float> %uint2float, <8 x float>* %ptr, align 4
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ret void
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}
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