mirror of
https://github.com/c64scene-ar/llvm-6502.git
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7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
109 lines
3.0 KiB
LLVM
109 lines
3.0 KiB
LLVM
;RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl | FileCheck %s
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;CHECK-LABEL: shift_16_i32
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;CHECK: vpsrld
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;CHECK: vpslld
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;CHECK: vpsrad
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;CHECK: ret
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define <16 x i32> @shift_16_i32(<16 x i32> %a) {
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%b = lshr <16 x i32> %a, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
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%c = shl <16 x i32> %b, <i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12>
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%d = ashr <16 x i32> %c, <i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12>
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ret <16 x i32> %d;
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}
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;CHECK-LABEL: shift_8_i64
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;CHECK: vpsrlq
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;CHECK: vpsllq
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;CHECK: vpsraq
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;CHECK: ret
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define <8 x i64> @shift_8_i64(<8 x i64> %a) {
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%b = lshr <8 x i64> %a, <i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1>
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%c = shl <8 x i64> %b, <i64 12, i64 12, i64 12, i64 12, i64 12, i64 12, i64 12, i64 12>
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%d = ashr <8 x i64> %c, <i64 12, i64 12, i64 12, i64 12, i64 12, i64 12, i64 12, i64 12>
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ret <8 x i64> %d;
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}
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; CHECK-LABEL: variable_shl4
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; CHECK: vpsllvq %zmm
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; CHECK: ret
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define <8 x i64> @variable_shl4(<8 x i64> %x, <8 x i64> %y) {
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%k = shl <8 x i64> %x, %y
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ret <8 x i64> %k
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}
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; CHECK-LABEL: variable_shl5
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; CHECK: vpsllvd %zmm
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; CHECK: ret
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define <16 x i32> @variable_shl5(<16 x i32> %x, <16 x i32> %y) {
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%k = shl <16 x i32> %x, %y
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ret <16 x i32> %k
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}
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; CHECK-LABEL: variable_srl0
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; CHECK: vpsrlvd
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; CHECK: ret
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define <16 x i32> @variable_srl0(<16 x i32> %x, <16 x i32> %y) {
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%k = lshr <16 x i32> %x, %y
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ret <16 x i32> %k
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}
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; CHECK-LABEL: variable_srl2
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; CHECK: psrlvq
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; CHECK: ret
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define <8 x i64> @variable_srl2(<8 x i64> %x, <8 x i64> %y) {
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%k = lshr <8 x i64> %x, %y
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ret <8 x i64> %k
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}
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; CHECK-LABEL: variable_sra1
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; CHECK: vpsravd
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; CHECK: ret
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define <16 x i32> @variable_sra1(<16 x i32> %x, <16 x i32> %y) {
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%k = ashr <16 x i32> %x, %y
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ret <16 x i32> %k
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}
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; CHECK-LABEL: variable_sra2
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; CHECK: vpsravq %zmm
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; CHECK: ret
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define <8 x i64> @variable_sra2(<8 x i64> %x, <8 x i64> %y) {
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%k = ashr <8 x i64> %x, %y
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ret <8 x i64> %k
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}
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; CHECK-LABEL: variable_sra01_load
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; CHECK: vpsravd (%
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; CHECK: ret
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define <16 x i32> @variable_sra01_load(<16 x i32> %x, <16 x i32>* %y) {
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%y1 = load <16 x i32>, <16 x i32>* %y
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%k = ashr <16 x i32> %x, %y1
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ret <16 x i32> %k
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}
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; CHECK-LABEL: variable_shl1_load
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; CHECK: vpsllvd (%
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; CHECK: ret
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define <16 x i32> @variable_shl1_load(<16 x i32> %x, <16 x i32>* %y) {
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%y1 = load <16 x i32>, <16 x i32>* %y
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%k = shl <16 x i32> %x, %y1
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ret <16 x i32> %k
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}
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; CHECK: variable_srl0_load
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; CHECK: vpsrlvd (%
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; CHECK: ret
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define <16 x i32> @variable_srl0_load(<16 x i32> %x, <16 x i32>* %y) {
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%y1 = load <16 x i32>, <16 x i32>* %y
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%k = lshr <16 x i32> %x, %y1
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ret <16 x i32> %k
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}
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; CHECK: variable_srl3_load
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; CHECK: vpsrlvq (%
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; CHECK: ret
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define <8 x i64> @variable_srl3_load(<8 x i64> %x, <8 x i64>* %y) {
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%y1 = load <8 x i64>, <8 x i64>* %y
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%k = lshr <8 x i64> %x, %y1
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ret <8 x i64> %k
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}
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