mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-21 18:29:45 +00:00
877ac0a034
This will make it easy to update as I change some parts of the X86 backend, makes it more clear what instruction differences are introduced, and I find it makes it a bit easier to read as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228095 91177308-0d34-0410-b5e6-96231b3b80d8
179 lines
5.3 KiB
LLVM
179 lines
5.3 KiB
LLVM
; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 < %s | FileCheck %s
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;
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; Verify that the DAGCombiner is able to fold a vector AND into a blend
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; if one of the operands to the AND is a vector of all constants, and each
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; constant element is either zero or all-ones.
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define <4 x i32> @test1(<4 x i32> %A) {
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; CHECK-LABEL: test1:
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; CHECK: # BB#0:
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; CHECK-NEXT: pxor %xmm1, %xmm1
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; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
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; CHECK-NEXT: retq
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%1 = and <4 x i32> %A, <i32 -1, i32 0, i32 0, i32 0>
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ret <4 x i32> %1
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}
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define <4 x i32> @test2(<4 x i32> %A) {
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; CHECK-LABEL: test2:
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; CHECK: # BB#0:
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; CHECK-NEXT: pxor %xmm1, %xmm1
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; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
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; CHECK-NEXT: retq
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%1 = and <4 x i32> %A, <i32 0, i32 -1, i32 0, i32 0>
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ret <4 x i32> %1
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}
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define <4 x i32> @test3(<4 x i32> %A) {
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; CHECK-LABEL: test3:
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; CHECK: # BB#0:
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; CHECK-NEXT: pxor %xmm1, %xmm1
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; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5],xmm1[6,7]
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; CHECK-NEXT: retq
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%1 = and <4 x i32> %A, <i32 0, i32 0, i32 -1, i32 0>
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ret <4 x i32> %1
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}
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define <4 x i32> @test4(<4 x i32> %A) {
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; CHECK-LABEL: test4:
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; CHECK: # BB#0:
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; CHECK-NEXT: pxor %xmm1, %xmm1
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; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3,4,5],xmm0[6,7]
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; CHECK-NEXT: retq
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%1 = and <4 x i32> %A, <i32 0, i32 0, i32 0, i32 -1>
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ret <4 x i32> %1
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}
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define <4 x i32> @test5(<4 x i32> %A) {
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; CHECK-LABEL: test5:
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; CHECK: # BB#0:
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; CHECK-NEXT: pxor %xmm1, %xmm1
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; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
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; CHECK-NEXT: retq
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%1 = and <4 x i32> %A, <i32 -1, i32 0, i32 -1, i32 0>
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ret <4 x i32> %1
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}
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define <4 x i32> @test6(<4 x i32> %A) {
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; CHECK-LABEL: test6:
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; CHECK: # BB#0:
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; CHECK-NEXT: pxor %xmm1, %xmm1
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; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5],xmm0[6,7]
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; CHECK-NEXT: retq
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%1 = and <4 x i32> %A, <i32 0, i32 -1, i32 0, i32 -1>
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ret <4 x i32> %1
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}
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define <4 x i32> @test7(<4 x i32> %A) {
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; CHECK-LABEL: test7:
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; CHECK: # BB#0:
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; CHECK-NEXT: pxor %xmm1, %xmm1
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; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]
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; CHECK-NEXT: retq
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%1 = and <4 x i32> %A, <i32 0, i32 0, i32 -1, i32 -1>
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ret <4 x i32> %1
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}
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define <4 x i32> @test8(<4 x i32> %A) {
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; CHECK-LABEL: test8:
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; CHECK: # BB#0:
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; CHECK-NEXT: pxor %xmm1, %xmm1
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; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5],xmm0[6,7]
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; CHECK-NEXT: retq
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%1 = and <4 x i32> %A, <i32 -1, i32 0, i32 0, i32 -1>
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ret <4 x i32> %1
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}
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define <4 x i32> @test9(<4 x i32> %A) {
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; CHECK-LABEL: test9:
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; CHECK: # BB#0:
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; CHECK-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero
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; CHECK-NEXT: retq
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%1 = and <4 x i32> %A, <i32 -1, i32 -1, i32 0, i32 0>
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ret <4 x i32> %1
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}
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define <4 x i32> @test10(<4 x i32> %A) {
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; CHECK-LABEL: test10:
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; CHECK: # BB#0:
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; CHECK-NEXT: pxor %xmm1, %xmm1
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; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5],xmm1[6,7]
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; CHECK-NEXT: retq
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%1 = and <4 x i32> %A, <i32 0, i32 -1, i32 -1, i32 0>
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ret <4 x i32> %1
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}
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define <4 x i32> @test11(<4 x i32> %A) {
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; CHECK-LABEL: test11:
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; CHECK: # BB#0:
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; CHECK-NEXT: pxor %xmm1, %xmm1
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; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5,6,7]
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; CHECK-NEXT: retq
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%1 = and <4 x i32> %A, <i32 0, i32 -1, i32 -1, i32 -1>
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ret <4 x i32> %1
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}
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define <4 x i32> @test12(<4 x i32> %A) {
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; CHECK-LABEL: test12:
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; CHECK: # BB#0:
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; CHECK-NEXT: pxor %xmm1, %xmm1
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; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5],xmm1[6,7]
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; CHECK-NEXT: retq
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%1 = and <4 x i32> %A, <i32 -1, i32 -1, i32 -1, i32 0>
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ret <4 x i32> %1
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}
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define <4 x i32> @test13(<4 x i32> %A) {
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; CHECK-LABEL: test13:
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; CHECK: # BB#0:
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; CHECK-NEXT: pxor %xmm1, %xmm1
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; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5],xmm0[6,7]
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; CHECK-NEXT: retq
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%1 = and <4 x i32> %A, <i32 -1, i32 -1, i32 0, i32 -1>
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ret <4 x i32> %1
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}
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define <4 x i32> @test14(<4 x i32> %A) {
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; CHECK-LABEL: test14:
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; CHECK: # BB#0:
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; CHECK-NEXT: pxor %xmm1, %xmm1
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; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5,6,7]
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; CHECK-NEXT: retq
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%1 = and <4 x i32> %A, <i32 -1, i32 0, i32 -1, i32 -1>
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ret <4 x i32> %1
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}
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define <4 x i32> @test15(<4 x i32> %A, <4 x i32> %B) {
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; CHECK-LABEL: test15:
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; CHECK: # BB#0:
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; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5,6,7]
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; CHECK-NEXT: retq
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%1 = and <4 x i32> %A, <i32 -1, i32 0, i32 -1, i32 -1>
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%2 = and <4 x i32> %B, <i32 0, i32 -1, i32 0, i32 0>
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%3 = or <4 x i32> %1, %2
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ret <4 x i32> %3
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}
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define <4 x i32> @test16(<4 x i32> %A, <4 x i32> %B) {
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; CHECK-LABEL: test16:
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; CHECK: # BB#0:
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; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
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; CHECK-NEXT: retq
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%1 = and <4 x i32> %A, <i32 -1, i32 0, i32 -1, i32 0>
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%2 = and <4 x i32> %B, <i32 0, i32 -1, i32 0, i32 -1>
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%3 = or <4 x i32> %1, %2
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ret <4 x i32> %3
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}
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define <4 x i32> @test17(<4 x i32> %A, <4 x i32> %B) {
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; CHECK-LABEL: test17:
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; CHECK: # BB#0:
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; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5],xmm0[6,7]
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; CHECK-NEXT: retq
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%1 = and <4 x i32> %A, <i32 0, i32 -1, i32 0, i32 -1>
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%2 = and <4 x i32> %B, <i32 -1, i32 0, i32 -1, i32 0>
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%3 = or <4 x i32> %1, %2
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ret <4 x i32> %3
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}
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