mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-21 18:29:45 +00:00
9836c47ea6
Added target specific combine rules to fold blend intrinsics according to the following rules: 1) fold(blend A, A, Mask) -> A; 2) fold(blend A, B, <allZeros>) -> A; 3) fold(blend A, B, <allOnes>) -> B. Added two new tests to verify that the new folding rules work for all the optimized blend intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208895 91177308-0d34-0410-b5e6-96231b3b80d8
120 lines
3.9 KiB
LLVM
120 lines
3.9 KiB
LLVM
; RUN: llc < %s -march=x86-64 -mcpu=corei7-avx | FileCheck %s
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define <4 x double> @test_x86_avx_blend_pd_256(<4 x double> %a0) {
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%1 = call <4 x double> @llvm.x86.avx.blend.pd.256(<4 x double> %a0, <4 x double> %a0, i32 7)
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ret <4 x double> %1
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}
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; CHECK-LABEL: test_x86_avx_blend_pd_256
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; CHECK-NOT: vblendpd
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; CHECK: ret
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define <8 x float> @test_x86_avx_blend_ps_256(<8 x float> %a0) {
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%1 = call <8 x float> @llvm.x86.avx.blend.ps.256(<8 x float> %a0, <8 x float> %a0, i32 7)
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ret <8 x float> %1
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}
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; CHECK-LABEL: test_x86_avx_blend_ps_256
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; CHECK-NOT: vblendps
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; CHECK: ret
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define <4 x double> @test_x86_avx_blendv_pd_256(<4 x double> %a0, <4 x double> %a1) {
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%1 = call <4 x double> @llvm.x86.avx.blendv.pd.256(<4 x double> %a0, <4 x double> %a0, <4 x double> %a1)
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ret <4 x double> %1
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}
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; CHECK-LABEL: test_x86_avx_blendv_pd_256
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; CHECK-NOT: vblendvpd
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; CHECK: ret
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define <8 x float> @test_x86_avx_blendv_ps_256(<8 x float> %a0, <8 x float> %a1) {
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%1 = call <8 x float> @llvm.x86.avx.blendv.ps.256(<8 x float> %a0, <8 x float> %a0, <8 x float> %a1)
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ret <8 x float> %1
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}
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; CHECK-LABEL: test_x86_avx_blendv_ps_256
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; CHECK-NOT: vblendvps
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; CHECK: ret
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define <4 x double> @test2_x86_avx_blend_pd_256(<4 x double> %a0, <4 x double> %a1) {
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%1 = call <4 x double> @llvm.x86.avx.blend.pd.256(<4 x double> %a0, <4 x double> %a1, i32 0)
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ret <4 x double> %1
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}
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; CHECK-LABEL: test2_x86_avx_blend_pd_256
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; CHECK-NOT: vblendpd
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; CHECK: ret
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define <8 x float> @test2_x86_avx_blend_ps_256(<8 x float> %a0, <8 x float> %a1) {
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%1 = call <8 x float> @llvm.x86.avx.blend.ps.256(<8 x float> %a0, <8 x float> %a1, i32 0)
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ret <8 x float> %1
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}
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; CHECK-LABEL: test2_x86_avx_blend_ps_256
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; CHECK-NOT: vblendps
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; CHECK: ret
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define <4 x double> @test2_x86_avx_blendv_pd_256(<4 x double> %a0, <4 x double> %a1) {
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%1 = call <4 x double> @llvm.x86.avx.blendv.pd.256(<4 x double> %a0, <4 x double> %a1, <4 x double> zeroinitializer)
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ret <4 x double> %1
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}
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; CHECK-LABEL: test2_x86_avx_blendv_pd_256
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; CHECK-NOT: vblendvpd
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; CHECK: ret
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define <8 x float> @test2_x86_avx_blendv_ps_256(<8 x float> %a0, <8 x float> %a1) {
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%1 = call <8 x float> @llvm.x86.avx.blendv.ps.256(<8 x float> %a0, <8 x float> %a1, <8 x float> zeroinitializer)
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ret <8 x float> %1
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}
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; CHECK-LABEL: test2_x86_avx_blendv_ps_256
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; CHECK-NOT: vblendvps
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; CHECK: ret
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define <4 x double> @test3_x86_avx_blend_pd_256(<4 x double> %a0, <4 x double> %a1) {
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%1 = call <4 x double> @llvm.x86.avx.blend.pd.256(<4 x double> %a0, <4 x double> %a1, i32 -1)
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ret <4 x double> %1
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}
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; CHECK-LABEL: test3_x86_avx_blend_pd_256
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; CHECK-NOT: vblendpd
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; CHECK: ret
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define <8 x float> @test3_x86_avx_blend_ps_256(<8 x float> %a0, <8 x float> %a1) {
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%1 = call <8 x float> @llvm.x86.avx.blend.ps.256(<8 x float> %a0, <8 x float> %a1, i32 -1)
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ret <8 x float> %1
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}
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; CHECK-LABEL: test3_x86_avx_blend_ps_256
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; CHECK-NOT: vblendps
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; CHECK: ret
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define <4 x double> @test3_x86_avx_blendv_pd_256(<4 x double> %a0, <4 x double> %a1) {
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%Mask = bitcast <4 x i64> <i64 -1, i64 -1, i64 -1, i64 -1> to <4 x double>
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%1 = call <4 x double> @llvm.x86.avx.blendv.pd.256(<4 x double> %a0, <4 x double> %a1, <4 x double> %Mask)
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ret <4 x double> %1
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}
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; CHECK-LABEL: test3_x86_avx_blendv_pd_256
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; CHECK-NOT: vblendvpd
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; CHECK: ret
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define <8 x float> @test3_x86_avx_blendv_ps_256(<8 x float> %a0, <8 x float> %a1) {
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%Mask = bitcast <4 x i64> <i64 -1, i64 -1, i64 -1, i64 -1> to <8 x float>
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%1 = call <8 x float> @llvm.x86.avx.blendv.ps.256(<8 x float> %a0, <8 x float> %a1, <8 x float> %Mask)
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ret <8 x float> %1
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}
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; CHECK-LABEL: test3_x86_avx_blendv_ps_256
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; CHECK-NOT: vblendvps
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; CHECK: ret
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declare <4 x double> @llvm.x86.avx.blend.pd.256(<4 x double>, <4 x double>, i32)
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declare <8 x float> @llvm.x86.avx.blend.ps.256(<8 x float>, <8 x float>, i32)
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declare <4 x double> @llvm.x86.avx.blendv.pd.256(<4 x double>, <4 x double>, <4 x double>)
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declare <8 x float> @llvm.x86.avx.blendv.ps.256(<8 x float>, <8 x float>, <8 x float>)
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