mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-21 18:29:45 +00:00
8b2b8a1835
This update was done with the following bash script:
find test/CodeGen -name "*.ll" | \
while read NAME; do
echo "$NAME"
if ! grep -q "^; *RUN: *llc.*debug" $NAME; then
TEMP=`mktemp -t temp`
cp $NAME $TEMP
sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \
while read FUNC; do
sed -i '' "s/;\(.*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP
done
sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP
sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP
sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP
sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP
mv $TEMP $NAME
fi
done
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186280 91177308-0d34-0410-b5e6-96231b3b80d8
286 lines
9.5 KiB
LLVM
286 lines
9.5 KiB
LLVM
; RUN: llc < %s -march=x86-64 -mattr=+sse3,-avx | FileCheck %s -check-prefix=SSE3
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; RUN: llc < %s -march=x86-64 -mattr=-sse3,+avx | FileCheck %s -check-prefix=AVX
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; SSE3-LABEL: haddpd1:
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; SSE3-NOT: vhaddpd
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; SSE3: haddpd
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; AVX-LABEL: haddpd1:
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; AVX: vhaddpd
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define <2 x double> @haddpd1(<2 x double> %x, <2 x double> %y) {
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%a = shufflevector <2 x double> %x, <2 x double> %y, <2 x i32> <i32 0, i32 2>
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%b = shufflevector <2 x double> %x, <2 x double> %y, <2 x i32> <i32 1, i32 3>
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%r = fadd <2 x double> %a, %b
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ret <2 x double> %r
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}
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; SSE3-LABEL: haddpd2:
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; SSE3-NOT: vhaddpd
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; SSE3: haddpd
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; AVX-LABEL: haddpd2:
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; AVX: vhaddpd
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define <2 x double> @haddpd2(<2 x double> %x, <2 x double> %y) {
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%a = shufflevector <2 x double> %x, <2 x double> %y, <2 x i32> <i32 1, i32 2>
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%b = shufflevector <2 x double> %y, <2 x double> %x, <2 x i32> <i32 2, i32 1>
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%r = fadd <2 x double> %a, %b
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ret <2 x double> %r
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}
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; SSE3-LABEL: haddpd3:
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; SSE3-NOT: vhaddpd
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; SSE3: haddpd
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; AVX-LABEL: haddpd3:
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; AVX: vhaddpd
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define <2 x double> @haddpd3(<2 x double> %x) {
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%a = shufflevector <2 x double> %x, <2 x double> undef, <2 x i32> <i32 0, i32 undef>
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%b = shufflevector <2 x double> %x, <2 x double> undef, <2 x i32> <i32 1, i32 undef>
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%r = fadd <2 x double> %a, %b
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ret <2 x double> %r
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}
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; SSE3-LABEL: haddps1:
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; SSE3-NOT: vhaddps
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; SSE3: haddps
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; AVX-LABEL: haddps1:
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; AVX: vhaddps
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define <4 x float> @haddps1(<4 x float> %x, <4 x float> %y) {
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%a = shufflevector <4 x float> %x, <4 x float> %y, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
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%b = shufflevector <4 x float> %x, <4 x float> %y, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
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%r = fadd <4 x float> %a, %b
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ret <4 x float> %r
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}
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; SSE3-LABEL: haddps2:
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; SSE3-NOT: vhaddps
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; SSE3: haddps
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; AVX-LABEL: haddps2:
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; AVX: vhaddps
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define <4 x float> @haddps2(<4 x float> %x, <4 x float> %y) {
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%a = shufflevector <4 x float> %x, <4 x float> %y, <4 x i32> <i32 1, i32 2, i32 5, i32 6>
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%b = shufflevector <4 x float> %y, <4 x float> %x, <4 x i32> <i32 4, i32 7, i32 0, i32 3>
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%r = fadd <4 x float> %a, %b
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ret <4 x float> %r
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}
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; SSE3-LABEL: haddps3:
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; SSE3-NOT: vhaddps
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; SSE3: haddps
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; AVX-LABEL: haddps3:
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; AVX: vhaddps
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define <4 x float> @haddps3(<4 x float> %x) {
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%a = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 undef, i32 2, i32 4, i32 6>
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%b = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 undef, i32 3, i32 5, i32 7>
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%r = fadd <4 x float> %a, %b
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ret <4 x float> %r
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}
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; SSE3-LABEL: haddps4:
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; SSE3-NOT: vhaddps
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; SSE3: haddps
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; AVX-LABEL: haddps4:
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; AVX: vhaddps
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define <4 x float> @haddps4(<4 x float> %x) {
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%a = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 0, i32 2, i32 undef, i32 undef>
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%b = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 1, i32 3, i32 undef, i32 undef>
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%r = fadd <4 x float> %a, %b
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ret <4 x float> %r
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}
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; SSE3-LABEL: haddps5:
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; SSE3-NOT: vhaddps
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; SSE3: haddps
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; AVX-LABEL: haddps5:
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; AVX: vhaddps
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define <4 x float> @haddps5(<4 x float> %x) {
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%a = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 0, i32 3, i32 undef, i32 undef>
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%b = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 1, i32 2, i32 undef, i32 undef>
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%r = fadd <4 x float> %a, %b
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ret <4 x float> %r
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}
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; SSE3-LABEL: haddps6:
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; SSE3-NOT: vhaddps
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; SSE3: haddps
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; AVX-LABEL: haddps6:
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; AVX: vhaddps
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define <4 x float> @haddps6(<4 x float> %x) {
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%a = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
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%b = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
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%r = fadd <4 x float> %a, %b
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ret <4 x float> %r
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}
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; SSE3-LABEL: haddps7:
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; SSE3-NOT: vhaddps
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; SSE3: haddps
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; AVX-LABEL: haddps7:
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; AVX: vhaddps
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define <4 x float> @haddps7(<4 x float> %x) {
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%a = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 undef, i32 3, i32 undef, i32 undef>
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%b = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 undef, i32 2, i32 undef, i32 undef>
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%r = fadd <4 x float> %a, %b
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ret <4 x float> %r
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}
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; SSE3-LABEL: hsubpd1:
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; SSE3-NOT: vhsubpd
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; SSE3: hsubpd
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; AVX-LABEL: hsubpd1:
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; AVX: vhsubpd
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define <2 x double> @hsubpd1(<2 x double> %x, <2 x double> %y) {
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%a = shufflevector <2 x double> %x, <2 x double> %y, <2 x i32> <i32 0, i32 2>
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%b = shufflevector <2 x double> %x, <2 x double> %y, <2 x i32> <i32 1, i32 3>
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%r = fsub <2 x double> %a, %b
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ret <2 x double> %r
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}
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; SSE3-LABEL: hsubpd2:
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; SSE3-NOT: vhsubpd
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; SSE3: hsubpd
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; AVX-LABEL: hsubpd2:
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; AVX: vhsubpd
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define <2 x double> @hsubpd2(<2 x double> %x) {
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%a = shufflevector <2 x double> %x, <2 x double> undef, <2 x i32> <i32 0, i32 undef>
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%b = shufflevector <2 x double> %x, <2 x double> undef, <2 x i32> <i32 1, i32 undef>
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%r = fsub <2 x double> %a, %b
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ret <2 x double> %r
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}
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; SSE3-LABEL: hsubps1:
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; SSE3-NOT: vhsubps
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; SSE3: hsubps
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; AVX-LABEL: hsubps1:
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; AVX: vhsubps
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define <4 x float> @hsubps1(<4 x float> %x, <4 x float> %y) {
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%a = shufflevector <4 x float> %x, <4 x float> %y, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
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%b = shufflevector <4 x float> %x, <4 x float> %y, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
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%r = fsub <4 x float> %a, %b
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ret <4 x float> %r
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}
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; SSE3-LABEL: hsubps2:
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; SSE3-NOT: vhsubps
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; SSE3: hsubps
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; AVX-LABEL: hsubps2:
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; AVX: vhsubps
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define <4 x float> @hsubps2(<4 x float> %x) {
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%a = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 undef, i32 2, i32 4, i32 6>
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%b = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 undef, i32 3, i32 5, i32 7>
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%r = fsub <4 x float> %a, %b
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ret <4 x float> %r
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}
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; SSE3-LABEL: hsubps3:
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; SSE3-NOT: vhsubps
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; SSE3: hsubps
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; AVX-LABEL: hsubps3:
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; AVX: vhsubps
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define <4 x float> @hsubps3(<4 x float> %x) {
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%a = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 0, i32 2, i32 undef, i32 undef>
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%b = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 1, i32 3, i32 undef, i32 undef>
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%r = fsub <4 x float> %a, %b
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ret <4 x float> %r
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}
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; SSE3-LABEL: hsubps4:
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; SSE3-NOT: vhsubps
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; SSE3: hsubps
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; AVX-LABEL: hsubps4:
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; AVX: vhsubps
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define <4 x float> @hsubps4(<4 x float> %x) {
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%a = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
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%b = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
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%r = fsub <4 x float> %a, %b
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ret <4 x float> %r
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}
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; SSE3-LABEL: vhaddps1:
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; SSE3-NOT: vhaddps
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; SSE3: haddps
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; SSE3: haddps
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; AVX-LABEL: vhaddps1:
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; AVX: vhaddps
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define <8 x float> @vhaddps1(<8 x float> %x, <8 x float> %y) {
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%a = shufflevector <8 x float> %x, <8 x float> %y, <8 x i32> <i32 0, i32 2, i32 8, i32 10, i32 4, i32 6, i32 12, i32 14>
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%b = shufflevector <8 x float> %x, <8 x float> %y, <8 x i32> <i32 1, i32 3, i32 9, i32 11, i32 5, i32 7, i32 13, i32 15>
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%r = fadd <8 x float> %a, %b
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ret <8 x float> %r
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}
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; SSE3-LABEL: vhaddps2:
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; SSE3-NOT: vhaddps
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; SSE3: haddps
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; SSE3: haddps
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; AVX-LABEL: vhaddps2:
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; AVX: vhaddps
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define <8 x float> @vhaddps2(<8 x float> %x, <8 x float> %y) {
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%a = shufflevector <8 x float> %x, <8 x float> %y, <8 x i32> <i32 1, i32 2, i32 9, i32 10, i32 5, i32 6, i32 13, i32 14>
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%b = shufflevector <8 x float> %y, <8 x float> %x, <8 x i32> <i32 8, i32 11, i32 0, i32 3, i32 12, i32 15, i32 4, i32 7>
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%r = fadd <8 x float> %a, %b
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ret <8 x float> %r
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}
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; SSE3-LABEL: vhaddps3:
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; SSE3-NOT: vhaddps
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; SSE3: haddps
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; SSE3: haddps
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; AVX-LABEL: vhaddps3:
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; AVX: vhaddps
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define <8 x float> @vhaddps3(<8 x float> %x) {
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%a = shufflevector <8 x float> %x, <8 x float> undef, <8 x i32> <i32 undef, i32 2, i32 8, i32 10, i32 4, i32 6, i32 undef, i32 14>
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%b = shufflevector <8 x float> %x, <8 x float> undef, <8 x i32> <i32 1, i32 3, i32 9, i32 undef, i32 5, i32 7, i32 13, i32 15>
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%r = fadd <8 x float> %a, %b
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ret <8 x float> %r
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}
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; SSE3-LABEL: vhsubps1:
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; SSE3-NOT: vhsubps
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; SSE3: hsubps
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; SSE3: hsubps
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; AVX-LABEL: vhsubps1:
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; AVX: vhsubps
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define <8 x float> @vhsubps1(<8 x float> %x, <8 x float> %y) {
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%a = shufflevector <8 x float> %x, <8 x float> %y, <8 x i32> <i32 0, i32 2, i32 8, i32 10, i32 4, i32 6, i32 12, i32 14>
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%b = shufflevector <8 x float> %x, <8 x float> %y, <8 x i32> <i32 1, i32 3, i32 9, i32 11, i32 5, i32 7, i32 13, i32 15>
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%r = fsub <8 x float> %a, %b
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ret <8 x float> %r
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}
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; SSE3-LABEL: vhsubps3:
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; SSE3-NOT: vhsubps
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; SSE3: hsubps
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; SSE3: hsubps
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; AVX-LABEL: vhsubps3:
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; AVX: vhsubps
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define <8 x float> @vhsubps3(<8 x float> %x) {
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%a = shufflevector <8 x float> %x, <8 x float> undef, <8 x i32> <i32 undef, i32 2, i32 8, i32 10, i32 4, i32 6, i32 undef, i32 14>
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%b = shufflevector <8 x float> %x, <8 x float> undef, <8 x i32> <i32 1, i32 3, i32 9, i32 undef, i32 5, i32 7, i32 13, i32 15>
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%r = fsub <8 x float> %a, %b
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ret <8 x float> %r
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}
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; SSE3-LABEL: vhaddpd1:
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; SSE3-NOT: vhaddpd
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; SSE3: haddpd
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; SSE3: haddpd
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; AVX-LABEL: vhaddpd1:
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; AVX: vhaddpd
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define <4 x double> @vhaddpd1(<4 x double> %x, <4 x double> %y) {
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%a = shufflevector <4 x double> %x, <4 x double> %y, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
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%b = shufflevector <4 x double> %x, <4 x double> %y, <4 x i32> <i32 1, i32 5, i32 3, i32 7>
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%r = fadd <4 x double> %a, %b
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ret <4 x double> %r
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}
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; SSE3-LABEL: vhsubpd1:
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; SSE3-NOT: vhsubpd
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; SSE3: hsubpd
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; SSE3: hsubpd
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; AVX-LABEL: vhsubpd1:
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; AVX: vhsubpd
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define <4 x double> @vhsubpd1(<4 x double> %x, <4 x double> %y) {
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%a = shufflevector <4 x double> %x, <4 x double> %y, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
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%b = shufflevector <4 x double> %x, <4 x double> %y, <4 x i32> <i32 1, i32 5, i32 3, i32 7>
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%r = fsub <4 x double> %a, %b
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ret <4 x double> %r
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}
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