mirror of
https://github.com/c64scene-ar/llvm-6502.git
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749e8fee34
This patch teaches the backend how to efficiently lower logical and arithmetic packed shifts on both SSE and AVX/AVX2 machines. When possible, instead of scalarizing a vector shift, the backend should try to expand the shift into a sequence of two packed shifts by immedate count followed by a MOVSS/MOVSD. Example (v4i32 (srl A, (build_vector < X, Y, Y, Y>))) Can be rewritten as: (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>))) [with X and Y ConstantInt] The advantage is that the two new shifts from the example would be lowered into X86ISD::VSRLI nodes. This is always cheaper than scalarizing the vector into four scalar shifts plus four pairs of vector insert/extract. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206316 91177308-0d34-0410-b5e6-96231b3b80d8
126 lines
2.9 KiB
LLVM
126 lines
2.9 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7-avx | FileCheck %s --check-prefix=CHECK --check-prefix=AVX
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; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=core2 | FileCheck %s --check-prefix=CHECK --check-prefix=SSE
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; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=core-avx2 | FileCheck %s --check-prefix=CHECK --check-prefix=AVX2
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; Verify that the following shifts are lowered into a sequence of two shifts plus
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; a blend. On pre-avx2 targets, instead of scalarizing logical and arithmetic
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; packed shift right by a constant build_vector the backend should always try to
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; emit a simpler sequence of two shifts + blend when possible.
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define <8 x i16> @test1(<8 x i16> %a) {
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%lshr = lshr <8 x i16> %a, <i16 3, i16 3, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2>
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ret <8 x i16> %lshr
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}
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; CHECK-LABEL: test1
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; SSE: psrlw
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; SSE-NEXT: psrlw
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; SSE-NEXT: movss
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; AVX: vpsrlw
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; AVX-NEXT: vpsrlw
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; AVX-NEXT: vmovss
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; AVX2: vpsrlw
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; AVX2-NEXT: vpsrlw
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; AVX2-NEXT: vmovss
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; CHECK: ret
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define <8 x i16> @test2(<8 x i16> %a) {
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%lshr = lshr <8 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 2, i16 2, i16 2, i16 2>
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ret <8 x i16> %lshr
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}
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; CHECK-LABEL: test2
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; SSE: psrlw
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; SSE-NEXT: psrlw
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; SSE-NEXT: movsd
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; AVX: vpsrlw
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; AVX-NEXT: vpsrlw
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; AVX-NEXT: vmovsd
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; AVX2: vpsrlw
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; AVX2-NEXT: vpsrlw
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; AVX2-NEXT: vmovsd
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; CHECK: ret
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define <4 x i32> @test3(<4 x i32> %a) {
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%lshr = lshr <4 x i32> %a, <i32 3, i32 2, i32 2, i32 2>
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ret <4 x i32> %lshr
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}
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; CHECK-LABEL: test3
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; SSE: psrld
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; SSE-NEXT: psrld
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; SSE-NEXT: movss
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; AVX: vpsrld
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; AVX-NEXT: vpsrld
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; AVX-NEXT: vmovss
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; AVX2: vpsrlvd
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; CHECK: ret
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define <4 x i32> @test4(<4 x i32> %a) {
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%lshr = lshr <4 x i32> %a, <i32 3, i32 3, i32 2, i32 2>
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ret <4 x i32> %lshr
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}
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; CHECK-LABEL: test4
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; SSE: psrld
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; SSE-NEXT: psrld
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; SSE-NEXT: movsd
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; AVX: vpsrld
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; AVX-NEXT: vpsrld
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; AVX-NEXT: vmovsd
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; AVX2: vpsrlvd
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; CHECK: ret
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define <8 x i16> @test5(<8 x i16> %a) {
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%lshr = ashr <8 x i16> %a, <i16 3, i16 3, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2>
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ret <8 x i16> %lshr
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}
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define <8 x i16> @test6(<8 x i16> %a) {
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%lshr = ashr <8 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 2, i16 2, i16 2, i16 2>
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ret <8 x i16> %lshr
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}
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; CHECK-LABEL: test6
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; SSE: psraw
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; SSE-NEXT: psraw
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; SSE-NEXT: movsd
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; AVX: vpsraw
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; AVX-NEXT: vpsraw
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; AVX-NEXT: vmovsd
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; AVX2: vpsraw
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; AVX2-NEXT: vpsraw
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; AVX2-NEXT: vmovsd
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; CHECK: ret
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define <4 x i32> @test7(<4 x i32> %a) {
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%lshr = ashr <4 x i32> %a, <i32 3, i32 2, i32 2, i32 2>
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ret <4 x i32> %lshr
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}
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; CHECK-LABEL: test7
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; SSE: psrad
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; SSE-NEXT: psrad
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; SSE-NEXT: movss
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; AVX: vpsrad
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; AVX-NEXT: vpsrad
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; AVX-NEXT: vmovss
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; AVX2: vpsravd
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; CHECK: ret
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define <4 x i32> @test8(<4 x i32> %a) {
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%lshr = ashr <4 x i32> %a, <i32 3, i32 3, i32 2, i32 2>
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ret <4 x i32> %lshr
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}
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; CHECK-LABEL: test8
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; SSE: psrad
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; SSE-NEXT: psrad
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; SSE-NEXT: movsd
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; AVX: vpsrad
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; AVX-NEXT: vpsrad
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; AVX-NEXT: vmovsd
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; AVX2: vpsravd
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; CHECK: ret
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