mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-21 18:29:45 +00:00
7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
124 lines
4.4 KiB
LLVM
124 lines
4.4 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=x86-64 -mattr=+sse4.1 | FileCheck %s --check-prefix=CHECK --check-prefix=SSE41
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=x86-64 -mattr=+avx2 | FileCheck %s --check-prefix=CHECK --check-prefix=AVX
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define <8 x i16> @test_llvm_x86_sse41_pmovsxbw(<16 x i8>* %a) {
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; CHECK-LABEL: test_llvm_x86_sse41_pmovsxbw
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; SSE41: pmovsxbw (%rdi), %xmm0
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; AVX: vpmovsxbw (%rdi), %xmm0
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%1 = load <16 x i8>, <16 x i8>* %a, align 1
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%2 = call <8 x i16> @llvm.x86.sse41.pmovsxbw(<16 x i8> %1)
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ret <8 x i16> %2
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}
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define <4 x i32> @test_llvm_x86_sse41_pmovsxbd(<16 x i8>* %a) {
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; CHECK-LABEL: test_llvm_x86_sse41_pmovsxbd
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; SSE41: pmovsxbd (%rdi), %xmm0
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; AVX: vpmovsxbd (%rdi), %xmm0
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%1 = load <16 x i8>, <16 x i8>* %a, align 1
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%2 = call <4 x i32> @llvm.x86.sse41.pmovsxbd(<16 x i8> %1)
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ret <4 x i32> %2
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}
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define <2 x i64> @test_llvm_x86_sse41_pmovsxbq(<16 x i8>* %a) {
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; CHECK-LABEL: test_llvm_x86_sse41_pmovsxbq
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; SSE41: pmovsxbq (%rdi), %xmm0
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; AVX: vpmovsxbq (%rdi), %xmm0
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%1 = load <16 x i8>, <16 x i8>* %a, align 1
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%2 = call <2 x i64> @llvm.x86.sse41.pmovsxbq(<16 x i8> %1)
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ret <2 x i64> %2
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}
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define <4 x i32> @test_llvm_x86_sse41_pmovsxwd(<8 x i16>* %a) {
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; CHECK-LABEL: test_llvm_x86_sse41_pmovsxwd
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; SSE41: pmovsxwd (%rdi), %xmm0
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; AVX: vpmovsxwd (%rdi), %xmm0
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%1 = load <8 x i16>, <8 x i16>* %a, align 1
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%2 = call <4 x i32> @llvm.x86.sse41.pmovsxwd(<8 x i16> %1)
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ret <4 x i32> %2
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}
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define <2 x i64> @test_llvm_x86_sse41_pmovsxwq(<8 x i16>* %a) {
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; CHECK-LABEL: test_llvm_x86_sse41_pmovsxwq
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; SSE41: pmovsxwq (%rdi), %xmm0
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; AVX: vpmovsxwq (%rdi), %xmm0
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%1 = load <8 x i16>, <8 x i16>* %a, align 1
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%2 = call <2 x i64> @llvm.x86.sse41.pmovsxwq(<8 x i16> %1)
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ret <2 x i64> %2
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}
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define <2 x i64> @test_llvm_x86_sse41_pmovsxdq(<4 x i32>* %a) {
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; CHECK-LABEL: test_llvm_x86_sse41_pmovsxdq
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; SSE41: pmovsxdq (%rdi), %xmm0
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; AVX: vpmovsxdq (%rdi), %xmm0
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%1 = load <4 x i32>, <4 x i32>* %a, align 1
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%2 = call <2 x i64> @llvm.x86.sse41.pmovsxdq(<4 x i32> %1)
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ret <2 x i64> %2
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}
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define <8 x i16> @test_llvm_x86_sse41_pmovzxbw(<16 x i8>* %a) {
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; CHECK-LABEL: test_llvm_x86_sse41_pmovzxbw
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; SSE41: pmovzxbw (%rdi), %xmm0
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; AVX: vpmovzxbw (%rdi), %xmm0
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%1 = load <16 x i8>, <16 x i8>* %a, align 1
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%2 = call <8 x i16> @llvm.x86.sse41.pmovzxbw(<16 x i8> %1)
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ret <8 x i16> %2
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}
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define <4 x i32> @test_llvm_x86_sse41_pmovzxbd(<16 x i8>* %a) {
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; CHECK-LABEL: test_llvm_x86_sse41_pmovzxbd
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; SSE41: pmovzxbd (%rdi), %xmm0
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; AVX: vpmovzxbd (%rdi), %xmm0
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%1 = load <16 x i8>, <16 x i8>* %a, align 1
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%2 = call <4 x i32> @llvm.x86.sse41.pmovzxbd(<16 x i8> %1)
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ret <4 x i32> %2
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}
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define <2 x i64> @test_llvm_x86_sse41_pmovzxbq(<16 x i8>* %a) {
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; CHECK-LABEL: test_llvm_x86_sse41_pmovzxbq
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; SSE41: pmovzxbq (%rdi), %xmm0
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; AVX: vpmovzxbq (%rdi), %xmm0
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%1 = load <16 x i8>, <16 x i8>* %a, align 1
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%2 = call <2 x i64> @llvm.x86.sse41.pmovzxbq(<16 x i8> %1)
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ret <2 x i64> %2
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}
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define <4 x i32> @test_llvm_x86_sse41_pmovzxwd(<8 x i16>* %a) {
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; CHECK-LABEL: test_llvm_x86_sse41_pmovzxwd
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; SSE41: pmovzxwd (%rdi), %xmm0
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; AVX: vpmovzxwd (%rdi), %xmm0
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%1 = load <8 x i16>, <8 x i16>* %a, align 1
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%2 = call <4 x i32> @llvm.x86.sse41.pmovzxwd(<8 x i16> %1)
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ret <4 x i32> %2
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}
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define <2 x i64> @test_llvm_x86_sse41_pmovzxwq(<8 x i16>* %a) {
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; CHECK-LABEL: test_llvm_x86_sse41_pmovzxwq
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; SSE41: pmovzxwq (%rdi), %xmm0
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; AVX: vpmovzxwq (%rdi), %xmm0
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%1 = load <8 x i16>, <8 x i16>* %a, align 1
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%2 = call <2 x i64> @llvm.x86.sse41.pmovzxwq(<8 x i16> %1)
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ret <2 x i64> %2
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}
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define <2 x i64> @test_llvm_x86_sse41_pmovzxdq(<4 x i32>* %a) {
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; CHECK-LABEL: test_llvm_x86_sse41_pmovzxdq
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; SSE41: pmovzxdq (%rdi), %xmm0
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; AVX: vpmovzxdq (%rdi), %xmm0
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%1 = load <4 x i32>, <4 x i32>* %a, align 1
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%2 = call <2 x i64> @llvm.x86.sse41.pmovzxdq(<4 x i32> %1)
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ret <2 x i64> %2
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}
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declare <2 x i64> @llvm.x86.sse41.pmovzxdq(<4 x i32>)
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declare <2 x i64> @llvm.x86.sse41.pmovzxwq(<8 x i16>)
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declare <4 x i32> @llvm.x86.sse41.pmovzxwd(<8 x i16>)
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declare <2 x i64> @llvm.x86.sse41.pmovzxbq(<16 x i8>)
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declare <4 x i32> @llvm.x86.sse41.pmovzxbd(<16 x i8>)
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declare <8 x i16> @llvm.x86.sse41.pmovzxbw(<16 x i8>)
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declare <2 x i64> @llvm.x86.sse41.pmovsxdq(<4 x i32>)
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declare <2 x i64> @llvm.x86.sse41.pmovsxwq(<8 x i16>)
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declare <4 x i32> @llvm.x86.sse41.pmovsxwd(<8 x i16>)
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declare <2 x i64> @llvm.x86.sse41.pmovsxbq(<16 x i8>)
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declare <4 x i32> @llvm.x86.sse41.pmovsxbd(<16 x i8>)
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declare <8 x i16> @llvm.x86.sse41.pmovsxbw(<16 x i8>)
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