llvm-6502/test/CodeGen/X86/subreg-to-reg-6.ll
David Blaikie 7c9c6ed761 [opaque pointer type] Add textual IR support for explicit type parameter to load instruction
Essentially the same as the GEP change in r230786.

A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)

import fileinput
import sys
import re

pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")

for line in sys.stdin:
  sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))

Reviewers: rafael, dexonsmith, grosser

Differential Revision: http://reviews.llvm.org/D7649

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-27 21:17:42 +00:00

30 lines
509 B
LLVM

; RUN: llc < %s -march=x86-64
define i64 @foo() nounwind {
entry:
%t0 = load i32, i32* null, align 8
switch i32 %t0, label %bb65 [
i32 16, label %bb
i32 12, label %bb56
]
bb:
br label %bb65
bb56:
unreachable
bb65:
%a = phi i64 [ 0, %bb ], [ 0, %entry ]
tail call void asm "", "{cx}"(i64 %a) nounwind
%t15 = and i64 %a, 4294967295
ret i64 %t15
}
define i64 @bar(i64 %t0) nounwind {
call void asm "", "{cx}"(i64 0) nounwind
%t1 = sub i64 0, %t0
%t2 = and i64 %t1, 4294967295
ret i64 %t2
}