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https://github.com/c64scene-ar/llvm-6502.git
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6a7770b7ae
This changes the SelectionDAG scheduling preference to source order. Soon, the SelectionDAG scheduler can be bypassed saving a nice chunk of compile time. Performance differences that result from this change are often a consequence of register coalescing. The register coalescer is far from perfect. Bugs can be filed for deficiencies. On x86 SandyBridge/Haswell, the source order schedule is often preserved, particularly for small blocks. Register pressure is generally improved over the SD scheduler's ILP mode. However, we are still able to handle large blocks that require latency hiding, unlike the SD scheduler's BURR mode. MI scheduler also attempts to discover the critical path in single-block loops and adjust heuristics accordingly. The MI scheduler relies on the new machine model. This is currently unimplemented for AVX, so we may not be generating the best code yet. Unit tests are updated so they don't depend on SD scheduling heuristics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192750 91177308-0d34-0410-b5e6-96231b3b80d8
72 lines
2.7 KiB
LLVM
72 lines
2.7 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-linux-gnu -tailcallopt -code-model=large -enable-misched=false | FileCheck %s
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declare fastcc i32 @callee(i32 %arg)
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define fastcc i32 @directcall(i32 %arg) {
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entry:
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; This is the large code model, so &callee may not fit into the jmp
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; instruction. Instead, stick it into a register.
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; CHECK: movabsq $callee, [[REGISTER:%r[a-z0-9]+]]
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; CHECK: jmpq *[[REGISTER]] # TAILCALL
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%res = tail call fastcc i32 @callee(i32 %arg)
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ret i32 %res
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}
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; Check that the register used for an indirect tail call doesn't
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; clobber any of the arguments.
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define fastcc i32 @indirect_manyargs(i32(i32,i32,i32,i32,i32,i32,i32)* %target) {
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; Adjust the stack to enter the function. (The amount of the
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; adjustment may change in the future, in which case the location of
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; the stack argument and the return adjustment will change too.)
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; CHECK: pushq
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; Put the call target into R11, which won't be clobbered while restoring
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; callee-saved registers and won't be used for passing arguments.
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; CHECK: movq %rdi, %rax
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; Pass the stack argument.
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; CHECK: movl $7, 16(%rsp)
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; Pass the register arguments, in the right registers.
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; CHECK: movl $1, %edi
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; CHECK: movl $2, %esi
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; CHECK: movl $3, %edx
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; CHECK: movl $4, %ecx
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; CHECK: movl $5, %r8d
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; CHECK: movl $6, %r9d
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; Adjust the stack to "return".
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; CHECK: popq
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; And tail-call to the target.
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; CHECK: jmpq *%rax # TAILCALL
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%res = tail call fastcc i32 %target(i32 1, i32 2, i32 3, i32 4, i32 5,
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i32 6, i32 7)
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ret i32 %res
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}
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; Check that the register used for a direct tail call doesn't clobber
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; any of the arguments.
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declare fastcc i32 @manyargs_callee(i32,i32,i32,i32,i32,i32,i32)
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define fastcc i32 @direct_manyargs() {
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; Adjust the stack to enter the function. (The amount of the
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; adjustment may change in the future, in which case the location of
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; the stack argument and the return adjustment will change too.)
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; CHECK: pushq
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; Pass the stack argument.
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; CHECK: movl $7, 16(%rsp)
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; This is the large code model, so &manyargs_callee may not fit into
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; the jmp instruction. Put it into a register which won't be clobbered
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; while restoring callee-saved registers and won't be used for passing
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; arguments.
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; CHECK: movabsq $manyargs_callee, %rax
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; Pass the register arguments, in the right registers.
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; CHECK: movl $1, %edi
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; CHECK: movl $2, %esi
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; CHECK: movl $3, %edx
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; CHECK: movl $4, %ecx
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; CHECK: movl $5, %r8d
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; CHECK: movl $6, %r9d
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; Adjust the stack to "return".
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; CHECK: popq
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; And tail-call to the target.
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; CHECK: jmpq *%rax # TAILCALL
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%res = tail call fastcc i32 @manyargs_callee(i32 1, i32 2, i32 3, i32 4,
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i32 5, i32 6, i32 7)
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ret i32 %res
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}
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