mirror of
https://github.com/c64scene-ar/llvm-6502.git
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6ec3395335
vector shift by immedate count (VSHLI/VSRLI/VSRAI) into a build_vector when the vector in input to the shift is a build_vector of all constants or UNDEFs. Target specific nodes for packed shifts by immediate count are in general introduced by function 'getTargetVShiftByConstNode' (in X86ISelLowering.cpp) when lowering shift operations, SSE/AVX immediate shift intrinsics and (only in very few cases) SIGN_EXTEND_INREG dag nodes. This patch adds extra rules for simplifying vector shifts inside function 'getTargetVShiftByConstNode'. Added file test/CodeGen/X86/vec_shift5.ll to verify that packed shifts by immediate are correctly folded into a build_vector when the input vector to the shift dag node is a vector of constants or undefs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198113 91177308-0d34-0410-b5e6-96231b3b80d8
161 lines
4.4 KiB
LLVM
161 lines
4.4 KiB
LLVM
; RUN: llc -march=x86-64 -mcpu=corei7 -mattr=-sse4.1 < %s | FileCheck %s
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; Verify that we correctly fold target specific packed vector shifts by
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; immediate count into a simple build_vector when the elements of the vector
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; in input to the packed shift are all constants or undef.
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define <8 x i16> @test1() {
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%1 = tail call <8 x i16> @llvm.x86.sse2.pslli.w(<8 x i16> <i16 1, i16 2, i16 4, i16 8, i16 1, i16 2, i16 4, i16 8>, i32 3)
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ret <8 x i16> %1
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}
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; CHECK-LABEL: test1
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; CHECK-NOT: psll
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; CHECK: movaps
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; CHECK-NEXT: ret
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define <8 x i16> @test2() {
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%1 = tail call <8 x i16> @llvm.x86.sse2.psrli.w(<8 x i16> <i16 4, i16 8, i16 16, i16 32, i16 4, i16 8, i16 16, i16 32>, i32 3)
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ret <8 x i16> %1
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}
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; CHECK-LABEL: test2
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; CHECK-NOT: psrl
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; CHECK: movaps
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; CHECK-NEXT: ret
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define <8 x i16> @test3() {
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%1 = tail call <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16> <i16 4, i16 8, i16 16, i16 32, i16 4, i16 8, i16 16, i16 32>, i32 3)
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ret <8 x i16> %1
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}
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; CHECK-LABEL: test3
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; CHECK-NOT: psra
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; CHECK: movaps
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; CHECK-NEXT: ret
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define <4 x i32> @test4() {
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%1 = tail call <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32> <i32 1, i32 2, i32 4, i32 8>, i32 3)
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ret <4 x i32> %1
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}
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; CHECK-LABEL: test4
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; CHECK-NOT: psll
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; CHECK: movaps
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; CHECK-NEXT: ret
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define <4 x i32> @test5() {
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%1 = tail call <4 x i32> @llvm.x86.sse2.psrli.d(<4 x i32> <i32 4, i32 8, i32 16, i32 32>, i32 3)
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ret <4 x i32> %1
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}
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; CHECK-LABEL: test5
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; CHECK-NOT: psrl
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; CHECK: movaps
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; CHECK-NEXT: ret
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define <4 x i32> @test6() {
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%1 = tail call <4 x i32> @llvm.x86.sse2.psrai.d(<4 x i32> <i32 4, i32 8, i32 16, i32 32>, i32 3)
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ret <4 x i32> %1
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}
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; CHECK-LABEL: test6
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; CHECK-NOT: psra
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; CHECK: movaps
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; CHECK-NEXT: ret
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define <2 x i64> @test7() {
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%1 = tail call <2 x i64> @llvm.x86.sse2.pslli.q(<2 x i64> <i64 1, i64 2>, i32 3)
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ret <2 x i64> %1
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}
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; CHECK-LABEL: test7
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; CHECK-NOT: psll
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; CHECK: movaps
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; CHECK-NEXT: ret
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define <2 x i64> @test8() {
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%1 = tail call <2 x i64> @llvm.x86.sse2.psrli.q(<2 x i64> <i64 8, i64 16>, i32 3)
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ret <2 x i64> %1
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}
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; CHECK-LABEL: test8
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; CHECK-NOT: psrl
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; CHECK: movaps
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; CHECK-NEXT: ret
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define <8 x i16> @test9() {
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%1 = tail call <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16> <i16 15, i16 8, i16 undef, i16 undef, i16 31, i16 undef, i16 64, i16 128>, i32 3)
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ret <8 x i16> %1
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}
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; CHECK-LABEL: test9
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; CHECK-NOT: psra
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; CHECK: movaps
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; CHECK-NEXT: ret
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define <4 x i32> @test10() {
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%1 = tail call <4 x i32> @llvm.x86.sse2.psrai.d(<4 x i32> <i32 undef, i32 8, i32 undef, i32 32>, i32 3)
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ret <4 x i32> %1
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}
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; CHECK-LABEL: test10
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; CHECK-NOT: psra
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; CHECK: movaps
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; CHECK-NEXT: ret
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define <2 x i64> @test11() {
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%1 = tail call <2 x i64> @llvm.x86.sse2.psrli.q(<2 x i64> <i64 undef, i64 31>, i32 3)
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ret <2 x i64> %1
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}
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; CHECK-LABEL: test11
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; CHECK-NOT: psrl
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; CHECK: movaps
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; CHECK-NEXT: ret
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define <8 x i16> @test12() {
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%1 = tail call <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16> <i16 15, i16 8, i16 undef, i16 undef, i16 31, i16 undef, i16 64, i16 128>, i32 3)
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ret <8 x i16> %1
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}
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; CHECK-LABEL: test12
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; CHECK-NOT: psra
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; CHECK: movaps
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; CHECK-NEXT: ret
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define <4 x i32> @test13() {
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%1 = tail call <4 x i32> @llvm.x86.sse2.psrli.d(<4 x i32> <i32 undef, i32 8, i32 undef, i32 32>, i32 3)
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ret <4 x i32> %1
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}
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; CHECK-LABEL: test13
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; CHECK-NOT: psrl
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; CHECK: movaps
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; CHECK-NEXT: ret
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define <8 x i16> @test14() {
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%1 = tail call <8 x i16> @llvm.x86.sse2.psrli.w(<8 x i16> <i16 15, i16 8, i16 undef, i16 undef, i16 31, i16 undef, i16 64, i16 128>, i32 3)
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ret <8 x i16> %1
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}
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; CHECK-LABEL: test14
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; CHECK-NOT: psrl
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; CHECK: movaps
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; CHECK-NEXT: ret
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define <4 x i32> @test15() {
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%1 = tail call <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32> <i32 undef, i32 8, i32 undef, i32 32>, i32 3)
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ret <4 x i32> %1
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}
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; CHECK-LABEL: test15
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; CHECK-NOT: psll
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; CHECK: movaps
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; CHECK-NEXT: ret
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define <2 x i64> @test16() {
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%1 = tail call <2 x i64> @llvm.x86.sse2.pslli.q(<2 x i64> <i64 undef, i64 31>, i32 3)
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ret <2 x i64> %1
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}
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; CHECK-LABEL: test16
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; CHECK-NOT: psll
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; CHECK: movaps
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; CHECK-NEXT: ret
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declare <8 x i16> @llvm.x86.sse2.pslli.w(<8 x i16>, i32)
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declare <8 x i16> @llvm.x86.sse2.psrli.w(<8 x i16>, i32)
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declare <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16>, i32)
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declare <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32>, i32)
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declare <4 x i32> @llvm.x86.sse2.psrli.d(<4 x i32>, i32)
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declare <4 x i32> @llvm.x86.sse2.psrai.d(<4 x i32>, i32)
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declare <2 x i64> @llvm.x86.sse2.pslli.q(<2 x i64>, i32)
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declare <2 x i64> @llvm.x86.sse2.psrli.q(<2 x i64>, i32)
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