llvm-6502/test/CodeGen/X86/vshift-2.ll
Quentin Colombet 75c9433b49 [DAGCombiner] insert_vector_elt: Avoid building a vector twice.
This patch prevents the following combine when the input vector is used more
than once.
insert_vector_elt (build_vector elt0, ..., eltN), NewEltIdx, idx
=>
build_vector elt0, ..., NewEltIdx, ..., eltN 

The reasons are:
- Building a vector may be expensive, so try to reuse the existing part of a
  vector instead of creating a new one (think big vectors).
- elt0 to eltN now have two users instead of one. This may prevent some other
  optimizations.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187396 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-30 00:24:09 +00:00

79 lines
2.3 KiB
LLVM

; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s
; test vector shifts converted to proper SSE2 vector shifts when the shift
; amounts are the same.
define void @shift1a(<2 x i64> %val, <2 x i64>* %dst) nounwind {
entry:
; CHECK-LABEL: shift1a:
; CHECK: psrlq
%lshr = lshr <2 x i64> %val, < i64 32, i64 32 >
store <2 x i64> %lshr, <2 x i64>* %dst
ret void
}
define void @shift1b(<2 x i64> %val, <2 x i64>* %dst, i64 %amt) nounwind {
entry:
; CHECK-LABEL: shift1b:
; CHECK: movd
; CHECK: psrlq
%0 = insertelement <2 x i64> undef, i64 %amt, i32 0
%1 = insertelement <2 x i64> %0, i64 %amt, i32 1
%lshr = lshr <2 x i64> %val, %1
store <2 x i64> %lshr, <2 x i64>* %dst
ret void
}
define void @shift2a(<4 x i32> %val, <4 x i32>* %dst) nounwind {
entry:
; CHECK-LABEL: shift2a:
; CHECK: psrld
%lshr = lshr <4 x i32> %val, < i32 17, i32 17, i32 17, i32 17 >
store <4 x i32> %lshr, <4 x i32>* %dst
ret void
}
define void @shift2b(<4 x i32> %val, <4 x i32>* %dst, i32 %amt) nounwind {
entry:
; CHECK-LABEL: shift2b:
; CHECK: movd
; CHECK: psrld
%0 = insertelement <4 x i32> undef, i32 %amt, i32 0
%1 = insertelement <4 x i32> %0, i32 %amt, i32 1
%2 = insertelement <4 x i32> %1, i32 %amt, i32 2
%3 = insertelement <4 x i32> %2, i32 %amt, i32 3
%lshr = lshr <4 x i32> %val, %3
store <4 x i32> %lshr, <4 x i32>* %dst
ret void
}
define void @shift3a(<8 x i16> %val, <8 x i16>* %dst) nounwind {
entry:
; CHECK-LABEL: shift3a:
; CHECK: psrlw
%lshr = lshr <8 x i16> %val, < i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5 >
store <8 x i16> %lshr, <8 x i16>* %dst
ret void
}
; properly zero extend the shift amount
define void @shift3b(<8 x i16> %val, <8 x i16>* %dst, i16 %amt) nounwind {
entry:
; CHECK-LABEL: shift3b:
; CHECK: movzwl
; CHECK: movd
; CHECK: psrlw
%0 = insertelement <8 x i16> undef, i16 %amt, i32 0
%1 = insertelement <8 x i16> %0, i16 %amt, i32 1
%2 = insertelement <8 x i16> %1, i16 %amt, i32 2
%3 = insertelement <8 x i16> %2, i16 %amt, i32 3
%4 = insertelement <8 x i16> %3, i16 %amt, i32 4
%5 = insertelement <8 x i16> %4, i16 %amt, i32 5
%6 = insertelement <8 x i16> %5, i16 %amt, i32 6
%7 = insertelement <8 x i16> %6, i16 %amt, i32 7
%lshr = lshr <8 x i16> %val, %7
store <8 x i16> %lshr, <8 x i16>* %dst
ret void
}