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https://github.com/c64scene-ar/llvm-6502.git
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d275e025d2
There are some operands which can take either immediates or registers and we were previously using different register class to distinguish between operands that could take immediates and those that could not. This patch switches to using RegisterOperands which should simplify the backend by reducing the number of register classes and also make it easier to implement the assembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225662 91177308-0d34-0410-b5e6-96231b3b80d8
167 lines
6.5 KiB
C++
167 lines
6.5 KiB
C++
//===-- SIDefines.h - SI Helper Macros ----------------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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/// \file
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//===----------------------------------------------------------------------===//
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#include "llvm/MC/MCInstrDesc.h"
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#ifndef LLVM_LIB_TARGET_R600_SIDEFINES_H
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#define LLVM_LIB_TARGET_R600_SIDEFINES_H
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namespace SIInstrFlags {
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// This needs to be kept in sync with the field bits in InstSI.
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enum {
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SALU = 1 << 3,
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VALU = 1 << 4,
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SOP1 = 1 << 5,
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SOP2 = 1 << 6,
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SOPC = 1 << 7,
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SOPK = 1 << 8,
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SOPP = 1 << 9,
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VOP1 = 1 << 10,
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VOP2 = 1 << 11,
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VOP3 = 1 << 12,
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VOPC = 1 << 13,
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MUBUF = 1 << 14,
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MTBUF = 1 << 15,
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SMRD = 1 << 16,
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DS = 1 << 17,
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MIMG = 1 << 18,
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FLAT = 1 << 19
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};
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}
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namespace llvm {
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namespace AMDGPU {
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enum OperandType {
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/// Operand with register or 32-bit immediate
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OPERAND_REG_IMM32 = llvm::MCOI::OPERAND_FIRST_TARGET,
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/// Operand with register or inline constant
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OPERAND_REG_INLINE_C
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};
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}
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}
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namespace SIInstrFlags {
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enum Flags {
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// First 4 bits are the instruction encoding
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VM_CNT = 1 << 0,
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EXP_CNT = 1 << 1,
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LGKM_CNT = 1 << 2
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};
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// v_cmp_class_* etc. use a 10-bit mask for what operation is checked.
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// The result is true if any of these tests are true.
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enum ClassFlags {
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S_NAN = 1 << 0, // Signaling NaN
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Q_NAN = 1 << 1, // Quiet NaN
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N_INFINITY = 1 << 2, // Negative infinity
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N_NORMAL = 1 << 3, // Negative normal
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N_SUBNORMAL = 1 << 4, // Negative subnormal
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N_ZERO = 1 << 5, // Negative zero
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P_ZERO = 1 << 6, // Positive zero
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P_SUBNORMAL = 1 << 7, // Positive subnormal
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P_NORMAL = 1 << 8, // Positive normal
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P_INFINITY = 1 << 9 // Positive infinity
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};
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}
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namespace SISrcMods {
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enum {
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NEG = 1 << 0,
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ABS = 1 << 1
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};
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}
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namespace SIOutMods {
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enum {
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NONE = 0,
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MUL2 = 1,
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MUL4 = 2,
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DIV2 = 3
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};
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}
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#define R_00B028_SPI_SHADER_PGM_RSRC1_PS 0x00B028
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#define R_00B02C_SPI_SHADER_PGM_RSRC2_PS 0x00B02C
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#define S_00B02C_EXTRA_LDS_SIZE(x) (((x) & 0xFF) << 8)
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#define R_00B128_SPI_SHADER_PGM_RSRC1_VS 0x00B128
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#define R_00B228_SPI_SHADER_PGM_RSRC1_GS 0x00B228
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#define R_00B848_COMPUTE_PGM_RSRC1 0x00B848
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#define S_00B028_VGPRS(x) (((x) & 0x3F) << 0)
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#define S_00B028_SGPRS(x) (((x) & 0x0F) << 6)
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#define R_00B84C_COMPUTE_PGM_RSRC2 0x00B84C
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#define S_00B84C_SCRATCH_EN(x) (((x) & 0x1) << 0)
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#define S_00B84C_USER_SGPR(x) (((x) & 0x1F) << 1)
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#define S_00B84C_TGID_X_EN(x) (((x) & 0x1) << 7)
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#define S_00B84C_TGID_Y_EN(x) (((x) & 0x1) << 8)
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#define S_00B84C_TGID_Z_EN(x) (((x) & 0x1) << 9)
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#define S_00B84C_TG_SIZE_EN(x) (((x) & 0x1) << 10)
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#define S_00B84C_TIDIG_COMP_CNT(x) (((x) & 0x03) << 11)
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#define S_00B84C_LDS_SIZE(x) (((x) & 0x1FF) << 15)
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#define R_0286CC_SPI_PS_INPUT_ENA 0x0286CC
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#define R_00B848_COMPUTE_PGM_RSRC1 0x00B848
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#define S_00B848_VGPRS(x) (((x) & 0x3F) << 0)
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#define G_00B848_VGPRS(x) (((x) >> 0) & 0x3F)
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#define C_00B848_VGPRS 0xFFFFFFC0
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#define S_00B848_SGPRS(x) (((x) & 0x0F) << 6)
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#define G_00B848_SGPRS(x) (((x) >> 6) & 0x0F)
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#define C_00B848_SGPRS 0xFFFFFC3F
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#define S_00B848_PRIORITY(x) (((x) & 0x03) << 10)
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#define G_00B848_PRIORITY(x) (((x) >> 10) & 0x03)
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#define C_00B848_PRIORITY 0xFFFFF3FF
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#define S_00B848_FLOAT_MODE(x) (((x) & 0xFF) << 12)
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#define G_00B848_FLOAT_MODE(x) (((x) >> 12) & 0xFF)
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#define C_00B848_FLOAT_MODE 0xFFF00FFF
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#define S_00B848_PRIV(x) (((x) & 0x1) << 20)
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#define G_00B848_PRIV(x) (((x) >> 20) & 0x1)
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#define C_00B848_PRIV 0xFFEFFFFF
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#define S_00B848_DX10_CLAMP(x) (((x) & 0x1) << 21)
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#define G_00B848_DX10_CLAMP(x) (((x) >> 21) & 0x1)
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#define C_00B848_DX10_CLAMP 0xFFDFFFFF
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#define S_00B848_DEBUG_MODE(x) (((x) & 0x1) << 22)
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#define G_00B848_DEBUG_MODE(x) (((x) >> 22) & 0x1)
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#define C_00B848_DEBUG_MODE 0xFFBFFFFF
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#define S_00B848_IEEE_MODE(x) (((x) & 0x1) << 23)
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#define G_00B848_IEEE_MODE(x) (((x) >> 23) & 0x1)
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#define C_00B848_IEEE_MODE 0xFF7FFFFF
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// Helpers for setting FLOAT_MODE
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#define FP_ROUND_ROUND_TO_NEAREST 0
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#define FP_ROUND_ROUND_TO_INF 1
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#define FP_ROUND_ROUND_TO_NEGINF 2
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#define FP_ROUND_ROUND_TO_ZERO 3
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// Bits 3:0 control rounding mode. 1:0 control single precision, 3:2 double
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// precision.
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#define FP_ROUND_MODE_SP(x) ((x) & 0x3)
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#define FP_ROUND_MODE_DP(x) (((x) & 0x3) << 2)
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#define FP_DENORM_FLUSH_IN_FLUSH_OUT 0
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#define FP_DENORM_FLUSH_OUT 1
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#define FP_DENORM_FLUSH_IN 2
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#define FP_DENORM_FLUSH_NONE 3
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// Bits 7:4 control denormal handling. 5:4 control single precision, 6:7 double
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// precision.
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#define FP_DENORM_MODE_SP(x) (((x) & 0x3) << 4)
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#define FP_DENORM_MODE_DP(x) (((x) & 0x3) << 6)
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#define R_00B860_COMPUTE_TMPRING_SIZE 0x00B860
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#define S_00B860_WAVESIZE(x) (((x) & 0x1FFF) << 12)
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#endif
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