Chandler Carruth 4b667ee436 [x86] Teach the new vector shuffle lowering to use AVX2 instructions for ... v4f64 and v8f32 shuffles when they are lane-crossing. We have fully general lane-crossing permutation functions in AVX2 that make this easy. Part of this also changes exactly when and how these vectors are split up when we don't have AVX2. This isn't always a win but it usually is a win, so on the balance I think its better. The primary regressions are all things that just need to be fixed anyways such as modeling when a blend can be completely accomplished via VINSERTF128, etc. Also, this highlights one of the few remaining big features: we do a really poor job of inserting elements into AVX registers efficiently. This completes almost all of the big tricks I have in mind for AVX2. The only things left that I plan to add: 1) element insertion smarts 2) palignr and other fairly specialized lowerings when they happen to apply git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218449 91177308-0d34-0410-b5e6-96231b3b80d8		2014-09-25 11:03:55 +00:00
..
AArch64	[FastISel][AArch64] Also allow folding of sign-/zero-extend and shift-left for booleans (i1).	2014-09-22 21:08:53 +00:00
ARM	Fix swift-atomics testcase	2014-09-23 23:18:01 +00:00
CPP
Generic
Hexagon
Inputs
Mips
MSP430
NVPTX
PowerPC	[Power] Use AtomicExpandPass for fence insertion, and use lwsync where appropriate	2014-09-23 20:46:49 +00:00
R600	R600/SI: Fix weird CHECK-DAG usage	2014-09-24 02:14:26 +00:00
SPARC
SystemZ
Thumb	[Thumb] Make load/store optimizer less conservative.	2014-09-24 16:35:50 +00:00
Thumb2
X86	[x86] Teach the new vector shuffle lowering to use AVX2 instructions for	2014-09-25 11:03:55 +00:00
XCore