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https://github.com/c64scene-ar/llvm-6502.git
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98f5cf8000
Fixes rv7x0 bug in Heaven reported here: https://bugs.freedesktop.org/show_bug.cgi?id=64257 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184116 91177308-0d34-0410-b5e6-96231b3b80d8
45 lines
2.0 KiB
LLVM
45 lines
2.0 KiB
LLVM
; RUN: llc < %s -march=r600 -show-mc-encoding -mcpu=rv710 | FileCheck %s
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; CHECK: TEX 9 @4 ; encoding: [0x04,0x00,0x00,0x00,0x00,0x04,0x88,0x80]
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define void @test(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
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%1 = call float @llvm.R600.load.input(i32 4)
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%2 = call float @llvm.R600.load.input(i32 5)
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%3 = call float @llvm.R600.load.input(i32 6)
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%4 = call float @llvm.R600.load.input(i32 7)
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%5 = insertelement <4 x float> undef, float %1, i32 0
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%6 = insertelement <4 x float> %5, float %2, i32 1
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%7 = insertelement <4 x float> %6, float %3, i32 2
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%8 = insertelement <4 x float> %7, float %4, i32 3
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%9 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %8, i32 0, i32 0, i32 1)
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%10 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %8, i32 1, i32 0, i32 1)
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%11 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %8, i32 2, i32 0, i32 1)
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%12 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %8, i32 3, i32 0, i32 1)
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%13 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %8, i32 4, i32 0, i32 1)
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%14 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %8, i32 5, i32 0, i32 1)
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%15 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %8, i32 6, i32 0, i32 1)
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%16 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %8, i32 7, i32 0, i32 1)
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%17 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %8, i32 8, i32 0, i32 1)
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%18 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %8, i32 9, i32 0, i32 1)
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%19 = fadd <4 x float> %9, %10
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%20 = fadd <4 x float> %19, %11
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%21 = fadd <4 x float> %20, %12
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%22 = fadd <4 x float> %21, %13
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%23 = fadd <4 x float> %22, %14
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%24 = fadd <4 x float> %23, %15
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%25 = fadd <4 x float> %24, %16
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%26 = fadd <4 x float> %25, %17
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%27 = fadd <4 x float> %26, %18
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call void @llvm.R600.store.swizzle(<4 x float> %27, i32 0, i32 2)
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ret void
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}
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declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32, i32) readnone
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; Function Attrs: readnone
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declare float @llvm.R600.load.input(i32) #1
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declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
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attributes #1 = { readnone }
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