Jim Laskey a99791886d Expose base register for DwarfWriter. Refactor code accordingly. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27225 91177308-0d34-0410-b5e6-96231b3b80d8		2006-03-28 13:48:33 +00:00
..
InstrSched
LiveVar
ModuloScheduling	Add explicit #includes of <iostream>	2006-01-22 23:41:00 +00:00
RegAlloc	There is no need to build an archive version of this library	2005-10-24 02:09:03 +00:00
.cvsignore	Ignore the burg output files.	2006-03-24 02:21:35 +00:00
DecomposeMultiDimRefs.cpp	Add explicit #includes of <iostream>	2006-01-22 23:41:00 +00:00
EmitBytecodeToAssembly.cpp
InternalGlobalMapper.cpp
MachineCodeForInstruction.cpp
MachineCodeForInstruction.h
MachineFunctionInfo.cpp
MachineFunctionInfo.h
MachineInstrAnnot.h
Makefile
MappingInfo.cpp
MappingInfo.h
SparcV9_F2.td
SparcV9_F3.td
SparcV9_F4.td
SparcV9.burg.in
SparcV9.td	PHI and INLINEASM are now built-in instructions provided by Target.td	2006-01-27 01:46:15 +00:00
SparcV9AsmPrinter.cpp	Adjust to MachineConstantPool interface change: instead of keeping a	2006-02-09 04:46:04 +00:00
SparcV9BurgISel.cpp	Eliminate IntrinsicLowering from TargetMachine.	2006-03-23 05:43:16 +00:00
SparcV9BurgISel.h
SparcV9CodeEmitter.cpp	Add explicit #includes of <iostream>	2006-01-22 22:53:01 +00:00
SparcV9CodeEmitter.h
SparcV9FrameInfo.cpp
SparcV9FrameInfo.h
SparcV9Instr.def
SparcV9InstrForest.h
SparcV9InstrInfo.h
SparcV9InstrInfo.td	PHI and INLINEASM are now built-in instructions provided by Target.td	2006-01-27 01:46:15 +00:00
SparcV9Internals.h
SparcV9JITInfo.cpp	Add explicit #includes of <iostream>	2006-01-22 22:53:01 +00:00
SparcV9JITInfo.h
SparcV9PeepholeOpts.cpp
SparcV9PreSelection.cpp
SparcV9PrologEpilogInserter.cpp
SparcV9RegClassInfo.cpp
SparcV9RegClassInfo.h
SparcV9RegInfo.cpp
SparcV9RegInfo.h
SparcV9RegisterInfo.cpp	Expose base register for DwarfWriter. Refactor code accordingly.	2006-03-28 13:48:33 +00:00
SparcV9RegisterInfo.h	Expose base register for DwarfWriter. Refactor code accordingly.	2006-03-28 13:48:33 +00:00
SparcV9RegisterInfo.td	Support multiple ValueTypes per RegisterClass, needed for upcoming vector	2005-12-01 04:51:06 +00:00
SparcV9Relocations.h
SparcV9SchedInfo.cpp
SparcV9StackSlots.cpp
SparcV9TargetMachine.cpp	Eliminate IntrinsicLowering from TargetMachine.	2006-03-23 05:43:16 +00:00
SparcV9TargetMachine.h	Eliminate IntrinsicLowering from TargetMachine.	2006-03-23 05:43:16 +00:00
SparcV9TmpInstr.cpp
SparcV9TmpInstr.h