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DAG scheduling during isel. Most new functionality is currently guarded by -enable-sched-cycles and -enable-sched-hazard. Added InstrItineraryData::IssueWidth field, currently derived from ARM itineraries, but could be initialized differently on other targets. Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is active, and if so how many cycles of state it holds. Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry into the scheduler's available queue. ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to get information about it's SUnits, provides RecedeCycle for bottom-up scheduling, correctly computes scoreboard depth, tracks IssueCount, and considers potential stall cycles when checking for hazards. ScheduleDAGRRList now models machine cycles and hazards (under flags). It tracks MinAvailableCycle, drives the hazard recognizer and priority queue's ready filter, manages a new PendingQueue, properly accounts for stall cycles, etc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122541 91177308-0d34-0410-b5e6-96231b3b80d8
432 lines
16 KiB
C++
432 lines
16 KiB
C++
//===-- TargetInstrInfoImpl.cpp - Target Instruction Information ----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the TargetInstrInfoImpl class, it just provides default
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// implementations of various methods.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineMemOperand.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/ScoreboardHazardRecognizer.h"
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#include "llvm/CodeGen/PseudoSourceValue.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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/// ReplaceTailWithBranchTo - Delete the instruction OldInst and everything
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/// after it, replacing it with an unconditional branch to NewDest.
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void
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TargetInstrInfoImpl::ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
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MachineBasicBlock *NewDest) const {
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MachineBasicBlock *MBB = Tail->getParent();
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// Remove all the old successors of MBB from the CFG.
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while (!MBB->succ_empty())
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MBB->removeSuccessor(MBB->succ_begin());
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// Remove all the dead instructions from the end of MBB.
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MBB->erase(Tail, MBB->end());
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// If MBB isn't immediately before MBB, insert a branch to it.
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if (++MachineFunction::iterator(MBB) != MachineFunction::iterator(NewDest))
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InsertBranch(*MBB, NewDest, 0, SmallVector<MachineOperand, 0>(),
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Tail->getDebugLoc());
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MBB->addSuccessor(NewDest);
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}
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// commuteInstruction - The default implementation of this method just exchanges
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// the two operands returned by findCommutedOpIndices.
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MachineInstr *TargetInstrInfoImpl::commuteInstruction(MachineInstr *MI,
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bool NewMI) const {
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const TargetInstrDesc &TID = MI->getDesc();
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bool HasDef = TID.getNumDefs();
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if (HasDef && !MI->getOperand(0).isReg())
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// No idea how to commute this instruction. Target should implement its own.
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return 0;
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unsigned Idx1, Idx2;
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if (!findCommutedOpIndices(MI, Idx1, Idx2)) {
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std::string msg;
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raw_string_ostream Msg(msg);
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Msg << "Don't know how to commute: " << *MI;
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report_fatal_error(Msg.str());
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}
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assert(MI->getOperand(Idx1).isReg() && MI->getOperand(Idx2).isReg() &&
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"This only knows how to commute register operands so far");
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unsigned Reg1 = MI->getOperand(Idx1).getReg();
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unsigned Reg2 = MI->getOperand(Idx2).getReg();
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bool Reg1IsKill = MI->getOperand(Idx1).isKill();
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bool Reg2IsKill = MI->getOperand(Idx2).isKill();
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bool ChangeReg0 = false;
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if (HasDef && MI->getOperand(0).getReg() == Reg1) {
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// Must be two address instruction!
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assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) &&
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"Expecting a two-address instruction!");
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Reg2IsKill = false;
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ChangeReg0 = true;
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}
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if (NewMI) {
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// Create a new instruction.
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unsigned Reg0 = HasDef
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? (ChangeReg0 ? Reg2 : MI->getOperand(0).getReg()) : 0;
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bool Reg0IsDead = HasDef ? MI->getOperand(0).isDead() : false;
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MachineFunction &MF = *MI->getParent()->getParent();
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if (HasDef)
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return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
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.addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
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.addReg(Reg2, getKillRegState(Reg2IsKill))
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.addReg(Reg1, getKillRegState(Reg2IsKill));
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else
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return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
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.addReg(Reg2, getKillRegState(Reg2IsKill))
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.addReg(Reg1, getKillRegState(Reg2IsKill));
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}
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if (ChangeReg0)
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MI->getOperand(0).setReg(Reg2);
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MI->getOperand(Idx2).setReg(Reg1);
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MI->getOperand(Idx1).setReg(Reg2);
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MI->getOperand(Idx2).setIsKill(Reg1IsKill);
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MI->getOperand(Idx1).setIsKill(Reg2IsKill);
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return MI;
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}
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/// findCommutedOpIndices - If specified MI is commutable, return the two
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/// operand indices that would swap value. Return true if the instruction
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/// is not in a form which this routine understands.
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bool TargetInstrInfoImpl::findCommutedOpIndices(MachineInstr *MI,
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unsigned &SrcOpIdx1,
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unsigned &SrcOpIdx2) const {
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const TargetInstrDesc &TID = MI->getDesc();
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if (!TID.isCommutable())
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return false;
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// This assumes v0 = op v1, v2 and commuting would swap v1 and v2. If this
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// is not true, then the target must implement this.
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SrcOpIdx1 = TID.getNumDefs();
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SrcOpIdx2 = SrcOpIdx1 + 1;
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if (!MI->getOperand(SrcOpIdx1).isReg() ||
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!MI->getOperand(SrcOpIdx2).isReg())
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// No idea.
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return false;
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return true;
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}
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bool TargetInstrInfoImpl::PredicateInstruction(MachineInstr *MI,
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const SmallVectorImpl<MachineOperand> &Pred) const {
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bool MadeChange = false;
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const TargetInstrDesc &TID = MI->getDesc();
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if (!TID.isPredicable())
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return false;
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for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) {
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if (TID.OpInfo[i].isPredicate()) {
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MachineOperand &MO = MI->getOperand(i);
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if (MO.isReg()) {
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MO.setReg(Pred[j].getReg());
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MadeChange = true;
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} else if (MO.isImm()) {
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MO.setImm(Pred[j].getImm());
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MadeChange = true;
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} else if (MO.isMBB()) {
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MO.setMBB(Pred[j].getMBB());
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MadeChange = true;
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}
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++j;
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}
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}
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return MadeChange;
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}
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void TargetInstrInfoImpl::reMaterialize(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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unsigned DestReg,
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unsigned SubIdx,
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const MachineInstr *Orig,
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const TargetRegisterInfo &TRI) const {
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MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
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MI->substituteRegister(MI->getOperand(0).getReg(), DestReg, SubIdx, TRI);
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MBB.insert(I, MI);
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}
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bool TargetInstrInfoImpl::produceSameValue(const MachineInstr *MI0,
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const MachineInstr *MI1) const {
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return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs);
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}
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MachineInstr *TargetInstrInfoImpl::duplicate(MachineInstr *Orig,
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MachineFunction &MF) const {
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assert(!Orig->getDesc().isNotDuplicable() &&
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"Instruction cannot be duplicated");
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return MF.CloneMachineInstr(Orig);
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}
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// If the COPY instruction in MI can be folded to a stack operation, return
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// the register class to use.
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static const TargetRegisterClass *canFoldCopy(const MachineInstr *MI,
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unsigned FoldIdx) {
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assert(MI->isCopy() && "MI must be a COPY instruction");
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if (MI->getNumOperands() != 2)
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return 0;
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assert(FoldIdx<2 && "FoldIdx refers no nonexistent operand");
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const MachineOperand &FoldOp = MI->getOperand(FoldIdx);
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const MachineOperand &LiveOp = MI->getOperand(1-FoldIdx);
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if (FoldOp.getSubReg() || LiveOp.getSubReg())
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return 0;
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unsigned FoldReg = FoldOp.getReg();
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unsigned LiveReg = LiveOp.getReg();
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assert(TargetRegisterInfo::isVirtualRegister(FoldReg) &&
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"Cannot fold physregs");
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const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
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const TargetRegisterClass *RC = MRI.getRegClass(FoldReg);
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if (TargetRegisterInfo::isPhysicalRegister(LiveOp.getReg()))
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return RC->contains(LiveOp.getReg()) ? RC : 0;
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const TargetRegisterClass *LiveRC = MRI.getRegClass(LiveReg);
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if (RC == LiveRC || RC->hasSubClass(LiveRC))
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return RC;
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// FIXME: Allow folding when register classes are memory compatible.
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return 0;
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}
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bool TargetInstrInfoImpl::
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canFoldMemoryOperand(const MachineInstr *MI,
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const SmallVectorImpl<unsigned> &Ops) const {
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return MI->isCopy() && Ops.size() == 1 && canFoldCopy(MI, Ops[0]);
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}
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/// foldMemoryOperand - Attempt to fold a load or store of the specified stack
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/// slot into the specified machine instruction for the specified operand(s).
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/// If this is possible, a new instruction is returned with the specified
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/// operand folded, otherwise NULL is returned. The client is responsible for
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/// removing the old instruction and adding the new one in the instruction
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/// stream.
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MachineInstr*
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TargetInstrInfo::foldMemoryOperand(MachineBasicBlock::iterator MI,
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const SmallVectorImpl<unsigned> &Ops,
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int FI) const {
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unsigned Flags = 0;
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for (unsigned i = 0, e = Ops.size(); i != e; ++i)
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if (MI->getOperand(Ops[i]).isDef())
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Flags |= MachineMemOperand::MOStore;
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else
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Flags |= MachineMemOperand::MOLoad;
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MachineBasicBlock *MBB = MI->getParent();
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assert(MBB && "foldMemoryOperand needs an inserted instruction");
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MachineFunction &MF = *MBB->getParent();
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// Ask the target to do the actual folding.
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if (MachineInstr *NewMI = foldMemoryOperandImpl(MF, MI, Ops, FI)) {
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// Add a memory operand, foldMemoryOperandImpl doesn't do that.
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assert((!(Flags & MachineMemOperand::MOStore) ||
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NewMI->getDesc().mayStore()) &&
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"Folded a def to a non-store!");
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assert((!(Flags & MachineMemOperand::MOLoad) ||
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NewMI->getDesc().mayLoad()) &&
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"Folded a use to a non-load!");
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const MachineFrameInfo &MFI = *MF.getFrameInfo();
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assert(MFI.getObjectOffset(FI) != -1);
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MachineMemOperand *MMO =
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MF.getMachineMemOperand(
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MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
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Flags, MFI.getObjectSize(FI),
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MFI.getObjectAlignment(FI));
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NewMI->addMemOperand(MF, MMO);
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// FIXME: change foldMemoryOperandImpl semantics to also insert NewMI.
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return MBB->insert(MI, NewMI);
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}
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// Straight COPY may fold as load/store.
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if (!MI->isCopy() || Ops.size() != 1)
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return 0;
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const TargetRegisterClass *RC = canFoldCopy(MI, Ops[0]);
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if (!RC)
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return 0;
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const MachineOperand &MO = MI->getOperand(1-Ops[0]);
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MachineBasicBlock::iterator Pos = MI;
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const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
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if (Flags == MachineMemOperand::MOStore)
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storeRegToStackSlot(*MBB, Pos, MO.getReg(), MO.isKill(), FI, RC, TRI);
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else
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loadRegFromStackSlot(*MBB, Pos, MO.getReg(), FI, RC, TRI);
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return --Pos;
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}
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/// foldMemoryOperand - Same as the previous version except it allows folding
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/// of any load and store from / to any address, not just from a specific
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/// stack slot.
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MachineInstr*
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TargetInstrInfo::foldMemoryOperand(MachineBasicBlock::iterator MI,
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const SmallVectorImpl<unsigned> &Ops,
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MachineInstr* LoadMI) const {
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assert(LoadMI->getDesc().canFoldAsLoad() && "LoadMI isn't foldable!");
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#ifndef NDEBUG
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for (unsigned i = 0, e = Ops.size(); i != e; ++i)
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assert(MI->getOperand(Ops[i]).isUse() && "Folding load into def!");
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#endif
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MachineBasicBlock &MBB = *MI->getParent();
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MachineFunction &MF = *MBB.getParent();
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// Ask the target to do the actual folding.
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MachineInstr *NewMI = foldMemoryOperandImpl(MF, MI, Ops, LoadMI);
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if (!NewMI) return 0;
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NewMI = MBB.insert(MI, NewMI);
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// Copy the memoperands from the load to the folded instruction.
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NewMI->setMemRefs(LoadMI->memoperands_begin(),
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LoadMI->memoperands_end());
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return NewMI;
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}
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bool TargetInstrInfo::
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isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI,
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AliasAnalysis *AA) const {
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const MachineFunction &MF = *MI->getParent()->getParent();
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const MachineRegisterInfo &MRI = MF.getRegInfo();
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const TargetMachine &TM = MF.getTarget();
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const TargetInstrInfo &TII = *TM.getInstrInfo();
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const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
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// A load from a fixed stack slot can be rematerialized. This may be
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// redundant with subsequent checks, but it's target-independent,
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// simple, and a common case.
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int FrameIdx = 0;
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if (TII.isLoadFromStackSlot(MI, FrameIdx) &&
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MF.getFrameInfo()->isImmutableObjectIndex(FrameIdx))
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return true;
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const TargetInstrDesc &TID = MI->getDesc();
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// Avoid instructions obviously unsafe for remat.
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if (TID.hasUnmodeledSideEffects() || TID.isNotDuplicable() ||
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TID.mayStore())
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return false;
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// Avoid instructions which load from potentially varying memory.
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if (TID.mayLoad() && !MI->isInvariantLoad(AA))
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return false;
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// If any of the registers accessed are non-constant, conservatively assume
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// the instruction is not rematerializable.
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg()) continue;
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unsigned Reg = MO.getReg();
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if (Reg == 0)
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continue;
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// Check for a well-behaved physical register.
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if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
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if (MO.isUse()) {
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// If the physreg has no defs anywhere, it's just an ambient register
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// and we can freely move its uses. Alternatively, if it's allocatable,
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// it could get allocated to something with a def during allocation.
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if (!MRI.def_empty(Reg))
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return false;
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BitVector AllocatableRegs = TRI.getAllocatableSet(MF, 0);
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if (AllocatableRegs.test(Reg))
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return false;
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// Check for a def among the register's aliases too.
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for (const unsigned *Alias = TRI.getAliasSet(Reg); *Alias; ++Alias) {
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unsigned AliasReg = *Alias;
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if (!MRI.def_empty(AliasReg))
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return false;
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if (AllocatableRegs.test(AliasReg))
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return false;
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}
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} else {
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// A physreg def. We can't remat it.
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return false;
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}
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continue;
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}
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// Only allow one virtual-register def, and that in the first operand.
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if (MO.isDef() != (i == 0))
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return false;
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// For the def, it should be the only def of that register.
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if (MO.isDef() && (llvm::next(MRI.def_begin(Reg)) != MRI.def_end() ||
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MRI.isLiveIn(Reg)))
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return false;
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// Don't allow any virtual-register uses. Rematting an instruction with
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// virtual register uses would length the live ranges of the uses, which
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// is not necessarily a good idea, certainly not "trivial".
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if (MO.isUse())
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return false;
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}
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// Everything checked out.
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return true;
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}
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/// isSchedulingBoundary - Test if the given instruction should be
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/// considered a scheduling boundary. This primarily includes labels
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/// and terminators.
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bool TargetInstrInfoImpl::isSchedulingBoundary(const MachineInstr *MI,
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const MachineBasicBlock *MBB,
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const MachineFunction &MF) const{
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// Terminators and labels can't be scheduled around.
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if (MI->getDesc().isTerminator() || MI->isLabel())
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return true;
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// Don't attempt to schedule around any instruction that defines
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// a stack-oriented pointer, as it's unlikely to be profitable. This
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// saves compile time, because it doesn't require every single
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// stack slot reference to depend on the instruction that does the
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// modification.
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const TargetLowering &TLI = *MF.getTarget().getTargetLowering();
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if (MI->definesRegister(TLI.getStackPointerRegisterToSaveRestore()))
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return true;
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return false;
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}
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// Default implementation of CreateTargetPreRAHazardRecognizer.
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ScheduleHazardRecognizer *TargetInstrInfoImpl::
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CreateTargetHazardRecognizer(const TargetMachine *TM,
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const ScheduleDAG *DAG) const {
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// Dummy hazard recognizer allows all instructions to issue.
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return new ScheduleHazardRecognizer();
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}
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// Default implementation of CreateTargetPostRAHazardRecognizer.
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ScheduleHazardRecognizer *TargetInstrInfoImpl::
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CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
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const ScheduleDAG *DAG) const {
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return (ScheduleHazardRecognizer *)
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new ScoreboardHazardRecognizer(II, DAG, "post-RA-sched");
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}
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