mirror of
https://github.com/c64scene-ar/llvm-6502.git
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6812cd18aa
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78381 91177308-0d34-0410-b5e6-96231b3b80d8
441 lines
12 KiB
C++
441 lines
12 KiB
C++
//===-- X86AsmParser.cpp - Parse X86 assembly to MCInst instructions ------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "X86.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/Twine.h"
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#include "llvm/MC/MCAsmLexer.h"
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#include "llvm/MC/MCAsmParser.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCValue.h"
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#include "llvm/Support/SourceMgr.h"
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#include "llvm/Target/TargetRegistry.h"
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#include "llvm/Target/TargetAsmParser.h"
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using namespace llvm;
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namespace {
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struct X86Operand;
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class X86ATTAsmParser : public TargetAsmParser {
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MCAsmParser &Parser;
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private:
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MCAsmParser &getParser() const { return Parser; }
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MCAsmLexer &getLexer() const { return Parser.getLexer(); }
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void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
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bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
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bool ParseRegister(X86Operand &Op);
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bool ParseOperand(X86Operand &Op);
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bool ParseMemOperand(X86Operand &Op);
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/// @name Auto-generated Match Functions
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/// {
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bool MatchInstruction(SmallVectorImpl<X86Operand> &Operands,
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MCInst &Inst);
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bool MatchRegisterName(const StringRef &Name, unsigned &RegNo);
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/// }
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public:
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X86ATTAsmParser(const Target &T, MCAsmParser &_Parser)
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: TargetAsmParser(T), Parser(_Parser) {}
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virtual bool ParseInstruction(const StringRef &Name, MCInst &Inst);
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};
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} // end anonymous namespace
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namespace {
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/// X86Operand - Instances of this class represent a parsed X86 machine
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/// instruction.
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struct X86Operand {
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enum {
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Token,
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Register,
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Immediate,
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Memory
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} Kind;
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union {
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struct {
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const char *Data;
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unsigned Length;
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} Tok;
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struct {
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unsigned RegNo;
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} Reg;
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struct {
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MCValue Val;
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} Imm;
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struct {
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unsigned SegReg;
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MCValue Disp;
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unsigned BaseReg;
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unsigned IndexReg;
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unsigned Scale;
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} Mem;
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};
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StringRef getToken() const {
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assert(Kind == Token && "Invalid access!");
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return StringRef(Tok.Data, Tok.Length);
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}
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unsigned getReg() const {
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assert(Kind == Register && "Invalid access!");
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return Reg.RegNo;
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}
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const MCValue &getImm() const {
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assert(Kind == Immediate && "Invalid access!");
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return Imm.Val;
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}
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const MCValue &getMemDisp() const {
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assert(Kind == Memory && "Invalid access!");
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return Mem.Disp;
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}
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unsigned getMemSegReg() const {
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assert(Kind == Memory && "Invalid access!");
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return Mem.SegReg;
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}
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unsigned getMemBaseReg() const {
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assert(Kind == Memory && "Invalid access!");
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return Mem.BaseReg;
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}
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unsigned getMemIndexReg() const {
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assert(Kind == Memory && "Invalid access!");
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return Mem.IndexReg;
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}
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unsigned getMemScale() const {
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assert(Kind == Memory && "Invalid access!");
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return Mem.Scale;
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}
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bool isToken(const StringRef &Str) const {
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return Kind == Token && Str == getToken();
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}
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bool isImm() const { return Kind == Immediate; }
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bool isMem() const { return Kind == Memory; }
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bool isReg() const { return Kind == Register; }
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void addRegOperands(MCInst &Inst, unsigned N) {
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assert(N == 1 && "Invalid number of operands!");
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Inst.addOperand(MCOperand::CreateReg(getReg()));
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}
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void addImmOperands(MCInst &Inst, unsigned N) {
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assert(N == 1 && "Invalid number of operands!");
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Inst.addOperand(MCOperand::CreateMCValue(getImm()));
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}
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void addMemOperands(MCInst &Inst, unsigned N) {
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assert((N == 4 || N == 5) && "Invalid number of operands!");
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Inst.addOperand(MCOperand::CreateReg(getMemBaseReg()));
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Inst.addOperand(MCOperand::CreateImm(getMemScale()));
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Inst.addOperand(MCOperand::CreateReg(getMemIndexReg()));
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Inst.addOperand(MCOperand::CreateMCValue(getMemDisp()));
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// FIXME: What a hack.
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if (N == 5)
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Inst.addOperand(MCOperand::CreateReg(getMemSegReg()));
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}
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static X86Operand CreateToken(StringRef Str) {
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X86Operand Res;
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Res.Kind = Token;
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Res.Tok.Data = Str.data();
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Res.Tok.Length = Str.size();
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return Res;
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}
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static X86Operand CreateReg(unsigned RegNo) {
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X86Operand Res;
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Res.Kind = Register;
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Res.Reg.RegNo = RegNo;
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return Res;
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}
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static X86Operand CreateImm(MCValue Val) {
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X86Operand Res;
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Res.Kind = Immediate;
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Res.Imm.Val = Val;
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return Res;
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}
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static X86Operand CreateMem(unsigned SegReg, MCValue Disp, unsigned BaseReg,
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unsigned IndexReg, unsigned Scale) {
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// We should never just have a displacement, that would be an immediate.
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assert((SegReg || BaseReg || IndexReg) && "Invalid memory operand!");
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// The scale should always be one of {1,2,4,8}.
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assert(((Scale == 1 || Scale == 2 || Scale == 4 || Scale == 8)) &&
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"Invalid scale!");
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X86Operand Res;
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Res.Kind = Memory;
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Res.Mem.SegReg = SegReg;
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Res.Mem.Disp = Disp;
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Res.Mem.BaseReg = BaseReg;
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Res.Mem.IndexReg = IndexReg;
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Res.Mem.Scale = Scale;
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return Res;
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}
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};
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} // end anonymous namespace.
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bool X86ATTAsmParser::ParseRegister(X86Operand &Op) {
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const AsmToken &Tok = getLexer().getTok();
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assert(Tok.is(AsmToken::Register) && "Invalid token kind!");
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// FIXME: Validate register for the current architecture; we have to do
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// validation later, so maybe there is no need for this here.
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unsigned RegNo;
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assert(Tok.getString().startswith("%") && "Invalid register name!");
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if (MatchRegisterName(Tok.getString().substr(1), RegNo))
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return Error(Tok.getLoc(), "invalid register name");
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Op = X86Operand::CreateReg(RegNo);
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getLexer().Lex(); // Eat register token.
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return false;
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}
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bool X86ATTAsmParser::ParseOperand(X86Operand &Op) {
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switch (getLexer().getKind()) {
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default:
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return ParseMemOperand(Op);
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case AsmToken::Register:
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// FIXME: if a segment register, this could either be just the seg reg, or
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// the start of a memory operand.
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return ParseRegister(Op);
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case AsmToken::Dollar: {
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// $42 -> immediate.
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getLexer().Lex();
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MCValue Val;
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if (getParser().ParseRelocatableExpression(Val))
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return true;
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Op = X86Operand::CreateImm(Val);
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return false;
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}
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case AsmToken::Star:
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getLexer().Lex(); // Eat the star.
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if (getLexer().is(AsmToken::Register)) {
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if (ParseRegister(Op))
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return true;
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} else if (ParseMemOperand(Op))
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return true;
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// FIXME: Note the '*' in the operand for use by the matcher.
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return false;
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}
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}
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/// ParseMemOperand: segment: disp(basereg, indexreg, scale)
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bool X86ATTAsmParser::ParseMemOperand(X86Operand &Op) {
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// FIXME: If SegReg ':' (e.g. %gs:), eat and remember.
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unsigned SegReg = 0;
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// We have to disambiguate a parenthesized expression "(4+5)" from the start
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// of a memory operand with a missing displacement "(%ebx)" or "(,%eax)". The
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// only way to do this without lookahead is to eat the ( and see what is after
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// it.
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MCValue Disp = MCValue::get(0, 0, 0);
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if (getLexer().isNot(AsmToken::LParen)) {
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if (getParser().ParseRelocatableExpression(Disp)) return true;
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// After parsing the base expression we could either have a parenthesized
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// memory address or not. If not, return now. If so, eat the (.
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if (getLexer().isNot(AsmToken::LParen)) {
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// Unless we have a segment register, treat this as an immediate.
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if (SegReg)
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Op = X86Operand::CreateMem(SegReg, Disp, 0, 0, 1);
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else
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Op = X86Operand::CreateImm(Disp);
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return false;
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}
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// Eat the '('.
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getLexer().Lex();
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} else {
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// Okay, we have a '('. We don't know if this is an expression or not, but
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// so we have to eat the ( to see beyond it.
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getLexer().Lex(); // Eat the '('.
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if (getLexer().is(AsmToken::Register) || getLexer().is(AsmToken::Comma)) {
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// Nothing to do here, fall into the code below with the '(' part of the
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// memory operand consumed.
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} else {
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// It must be an parenthesized expression, parse it now.
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if (getParser().ParseParenRelocatableExpression(Disp))
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return true;
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// After parsing the base expression we could either have a parenthesized
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// memory address or not. If not, return now. If so, eat the (.
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if (getLexer().isNot(AsmToken::LParen)) {
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// Unless we have a segment register, treat this as an immediate.
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if (SegReg)
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Op = X86Operand::CreateMem(SegReg, Disp, 0, 0, 1);
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else
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Op = X86Operand::CreateImm(Disp);
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return false;
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}
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// Eat the '('.
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getLexer().Lex();
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}
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}
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// If we reached here, then we just ate the ( of the memory operand. Process
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// the rest of the memory operand.
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unsigned BaseReg = 0, IndexReg = 0, Scale = 1;
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if (getLexer().is(AsmToken::Register)) {
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if (ParseRegister(Op))
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return true;
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BaseReg = Op.getReg();
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}
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if (getLexer().is(AsmToken::Comma)) {
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getLexer().Lex(); // Eat the comma.
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// Following the comma we should have either an index register, or a scale
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// value. We don't support the later form, but we want to parse it
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// correctly.
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//
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// Not that even though it would be completely consistent to support syntax
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// like "1(%eax,,1)", the assembler doesn't.
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if (getLexer().is(AsmToken::Register)) {
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if (ParseRegister(Op))
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return true;
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IndexReg = Op.getReg();
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if (getLexer().isNot(AsmToken::RParen)) {
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// Parse the scale amount:
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// ::= ',' [scale-expression]
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if (getLexer().isNot(AsmToken::Comma))
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return true;
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getLexer().Lex(); // Eat the comma.
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if (getLexer().isNot(AsmToken::RParen)) {
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SMLoc Loc = getLexer().getTok().getLoc();
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int64_t ScaleVal;
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if (getParser().ParseAbsoluteExpression(ScaleVal))
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return true;
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// Validate the scale amount.
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if (ScaleVal != 1 && ScaleVal != 2 && ScaleVal != 4 && ScaleVal != 8)
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return Error(Loc, "scale factor in address must be 1, 2, 4 or 8");
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Scale = (unsigned)ScaleVal;
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}
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}
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} else if (getLexer().isNot(AsmToken::RParen)) {
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// Otherwise we have the unsupported form of a scale amount without an
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// index.
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SMLoc Loc = getLexer().getTok().getLoc();
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int64_t Value;
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if (getParser().ParseAbsoluteExpression(Value))
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return true;
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return Error(Loc, "cannot have scale factor without index register");
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}
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}
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// Ok, we've eaten the memory operand, verify we have a ')' and eat it too.
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if (getLexer().isNot(AsmToken::RParen))
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return Error(getLexer().getTok().getLoc(),
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"unexpected token in memory operand");
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getLexer().Lex(); // Eat the ')'.
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Op = X86Operand::CreateMem(SegReg, Disp, BaseReg, IndexReg, Scale);
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return false;
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}
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bool X86ATTAsmParser::ParseInstruction(const StringRef &Name, MCInst &Inst) {
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SmallVector<X86Operand, 4> Operands;
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Operands.push_back(X86Operand::CreateToken(Name));
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SMLoc Loc = getLexer().getTok().getLoc();
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if (getLexer().isNot(AsmToken::EndOfStatement)) {
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// Read the first operand.
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Operands.push_back(X86Operand());
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if (ParseOperand(Operands.back()))
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return true;
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while (getLexer().is(AsmToken::Comma)) {
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getLexer().Lex(); // Eat the comma.
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// Parse and remember the operand.
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Operands.push_back(X86Operand());
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if (ParseOperand(Operands.back()))
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return true;
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}
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}
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if (!MatchInstruction(Operands, Inst))
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return false;
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// FIXME: We should give nicer diagnostics about the exact failure.
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// FIXME: For now we just treat unrecognized instructions as "warnings".
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Warning(Loc, "unrecognized instruction");
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return false;
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}
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// Force static initialization.
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extern "C" void LLVMInitializeX86AsmParser() {
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RegisterAsmParser<X86ATTAsmParser> X(TheX86_32Target);
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RegisterAsmParser<X86ATTAsmParser> Y(TheX86_64Target);
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}
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// FIXME: Disabled for now, this is causing gcc-4.0 to run out of memory during
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// building.
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#if 0
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#include "X86GenAsmMatcher.inc"
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#else
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bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands,
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MCInst &Inst) {
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return false;
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}
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bool X86ATTAsmParser::MatchRegisterName(const StringRef &Name,
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unsigned &RegNo) {
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RegNo = 1;
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return false;
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}
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#endif
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