mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-09-07 01:54:50 +00:00
9de5d0dd42
- Cleaned up custom load/store logic, common code is now shared [see note below], cleaned up address modes - More test cases: various intrinsics, structure element access (load/store test), updated target data strings, indirect function calls. Note: This patch contains a refactoring of the LoadSDNode and StoreSDNode structures: they now share a common base class, LSBaseSDNode, that provides an interface to their common functionality. There is some hackery to access the proper operand depending on the derived class; otherwise, to do a proper job would require finding and rearranging the SDOperands sent to StoreSDNode's constructor. The current refactor errs on the side of being conservatively and backwardly compatible while providing functionality that reduces redundant code for targets where loads and stores are custom-lowered. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45851 91177308-0d34-0410-b5e6-96231b3b80d8
153 lines
5.0 KiB
LLVM
153 lines
5.0 KiB
LLVM
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
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; RUN: grep eqv %t1.s | count 18 &&
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; RUN: grep xshw %t1.s | count 6 &&
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; RUN: grep xsbh %t1.s | count 3 &&
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; RUN: grep andi %t1.s | count 3
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; Test the 'eqv' instruction, whose boolean expression is:
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; (a & b) | (~a & ~b), which simplifies to
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; (a & b) | ~(a | b)
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; Alternatively, a ^ ~b, which the compiler will also match.
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; ModuleID = 'eqv.bc'
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target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
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target triple = "spu"
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define <4 x i32> @equiv_v4i32_1(<4 x i32> %arg1, <4 x i32> %arg2) {
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%A = and <4 x i32> %arg1, %arg2 ; <<4 x i32>> [#uses=1]
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%B = or <4 x i32> %arg1, %arg2 ; <<4 x i32>> [#uses=1]
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%Bnot = xor <4 x i32> %B, < i32 -1, i32 -1, i32 -1, i32 -1 > ; <<4 x i32>> [#uses=1]
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%C = or <4 x i32> %A, %Bnot ; <<4 x i32>> [#uses=1]
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ret <4 x i32> %C
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}
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define <4 x i32> @equiv_v4i32_2(<4 x i32> %arg1, <4 x i32> %arg2) {
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%B = or <4 x i32> %arg1, %arg2 ; <<4 x i32>> [#uses=1]
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%Bnot = xor <4 x i32> %B, < i32 -1, i32 -1, i32 -1, i32 -1 > ; <<4 x i32>> [#uses=1]
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%A = and <4 x i32> %arg1, %arg2 ; <<4 x i32>> [#uses=1]
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%C = or <4 x i32> %A, %Bnot ; <<4 x i32>> [#uses=1]
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ret <4 x i32> %C
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}
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define <4 x i32> @equiv_v4i32_3(<4 x i32> %arg1, <4 x i32> %arg2) {
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%B = or <4 x i32> %arg1, %arg2 ; <<4 x i32>> [#uses=1]
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%A = and <4 x i32> %arg1, %arg2 ; <<4 x i32>> [#uses=1]
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%Bnot = xor <4 x i32> %B, < i32 -1, i32 -1, i32 -1, i32 -1 > ; <<4 x i32>> [#uses=1]
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%C = or <4 x i32> %A, %Bnot ; <<4 x i32>> [#uses=1]
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ret <4 x i32> %C
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}
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define <4 x i32> @equiv_v4i32_4(<4 x i32> %arg1, <4 x i32> %arg2) {
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%arg2not = xor <4 x i32> %arg2, < i32 -1, i32 -1, i32 -1, i32 -1 > ; <<4 x i32>> [#uses=1]
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%C = xor <4 x i32> %arg1, %arg2not
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ret <4 x i32> %C
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}
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define i32 @equiv_i32_1(i32 %arg1, i32 %arg2) {
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%A = and i32 %arg1, %arg2 ; <i32> [#uses=1]
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%B = or i32 %arg1, %arg2 ; <i32> [#uses=1]
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%Bnot = xor i32 %B, -1 ; <i32> [#uses=1]
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%C = or i32 %A, %Bnot ; <i32> [#uses=1]
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ret i32 %C
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}
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define i32 @equiv_i32_2(i32 %arg1, i32 %arg2) {
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%B = or i32 %arg1, %arg2 ; <i32> [#uses=1]
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%Bnot = xor i32 %B, -1 ; <i32> [#uses=1]
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%A = and i32 %arg1, %arg2 ; <i32> [#uses=1]
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%C = or i32 %A, %Bnot ; <i32> [#uses=1]
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ret i32 %C
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}
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define i32 @equiv_i32_3(i32 %arg1, i32 %arg2) {
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%B = or i32 %arg1, %arg2 ; <i32> [#uses=1]
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%A = and i32 %arg1, %arg2 ; <i32> [#uses=1]
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%Bnot = xor i32 %B, -1 ; <i32> [#uses=1]
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%C = or i32 %A, %Bnot ; <i32> [#uses=1]
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ret i32 %C
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}
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define i32 @equiv_i32_4(i32 %arg1, i32 %arg2) {
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%arg2not = xor i32 %arg2, -1
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%C = xor i32 %arg1, %arg2not
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ret i32 %C
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}
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define i32 @equiv_i32_5(i32 %arg1, i32 %arg2) {
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%arg1not = xor i32 %arg1, -1
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%C = xor i32 %arg2, %arg1not
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ret i32 %C
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}
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define i16 @equiv_i16_1(i16 signext %arg1, i16 signext %arg2) signext {
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%A = and i16 %arg1, %arg2 ; <i16> [#uses=1]
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%B = or i16 %arg1, %arg2 ; <i16> [#uses=1]
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%Bnot = xor i16 %B, -1 ; <i16> [#uses=1]
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%C = or i16 %A, %Bnot ; <i16> [#uses=1]
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ret i16 %C
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}
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define i16 @equiv_i16_2(i16 signext %arg1, i16 signext %arg2) signext {
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%B = or i16 %arg1, %arg2 ; <i16> [#uses=1]
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%Bnot = xor i16 %B, -1 ; <i16> [#uses=1]
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%A = and i16 %arg1, %arg2 ; <i16> [#uses=1]
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%C = or i16 %A, %Bnot ; <i16> [#uses=1]
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ret i16 %C
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}
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define i16 @equiv_i16_3(i16 signext %arg1, i16 signext %arg2) signext {
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%B = or i16 %arg1, %arg2 ; <i16> [#uses=1]
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%A = and i16 %arg1, %arg2 ; <i16> [#uses=1]
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%Bnot = xor i16 %B, -1 ; <i16> [#uses=1]
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%C = or i16 %A, %Bnot ; <i16> [#uses=1]
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ret i16 %C
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}
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define i8 @equiv_i8_1(i8 signext %arg1, i8 signext %arg2) signext {
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%A = and i8 %arg1, %arg2 ; <i8> [#uses=1]
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%B = or i8 %arg1, %arg2 ; <i8> [#uses=1]
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%Bnot = xor i8 %B, -1 ; <i8> [#uses=1]
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%C = or i8 %A, %Bnot ; <i8> [#uses=1]
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ret i8 %C
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}
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define i8 @equiv_i8_2(i8 signext %arg1, i8 signext %arg2) signext {
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%B = or i8 %arg1, %arg2 ; <i8> [#uses=1]
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%Bnot = xor i8 %B, -1 ; <i8> [#uses=1]
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%A = and i8 %arg1, %arg2 ; <i8> [#uses=1]
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%C = or i8 %A, %Bnot ; <i8> [#uses=1]
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ret i8 %C
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}
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define i8 @equiv_i8_3(i8 signext %arg1, i8 signext %arg2) signext {
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%B = or i8 %arg1, %arg2 ; <i8> [#uses=1]
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%A = and i8 %arg1, %arg2 ; <i8> [#uses=1]
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%Bnot = xor i8 %B, -1 ; <i8> [#uses=1]
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%C = or i8 %A, %Bnot ; <i8> [#uses=1]
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ret i8 %C
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}
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define i8 @equiv_u8_1(i8 zeroext %arg1, i8 zeroext %arg2) zeroext {
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%A = and i8 %arg1, %arg2 ; <i8> [#uses=1]
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%B = or i8 %arg1, %arg2 ; <i8> [#uses=1]
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%Bnot = xor i8 %B, -1 ; <i8> [#uses=1]
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%C = or i8 %A, %Bnot ; <i8> [#uses=1]
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ret i8 %C
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}
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define i8 @equiv_u8_2(i8 zeroext %arg1, i8 zeroext %arg2) zeroext {
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%B = or i8 %arg1, %arg2 ; <i8> [#uses=1]
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%Bnot = xor i8 %B, -1 ; <i8> [#uses=1]
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%A = and i8 %arg1, %arg2 ; <i8> [#uses=1]
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%C = or i8 %A, %Bnot ; <i8> [#uses=1]
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ret i8 %C
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}
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define i8 @equiv_u8_3(i8 zeroext %arg1, i8 zeroext %arg2) zeroext {
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%B = or i8 %arg1, %arg2 ; <i8> [#uses=1]
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%A = and i8 %arg1, %arg2 ; <i8> [#uses=1]
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%Bnot = xor i8 %B, -1 ; <i8> [#uses=1]
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%C = or i8 %A, %Bnot ; <i8> [#uses=1]
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ret i8 %C
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}
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