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https://github.com/c64scene-ar/llvm-6502.git
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dcf2420b07
Otherwise it will try to use SSE patterns and fail horribly if sse is disabled. Fixes PR14035. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165377 91177308-0d34-0410-b5e6-96231b3b80d8
452 lines
7.5 KiB
LLVM
452 lines
7.5 KiB
LLVM
; RUN: llc -march x86 -mcpu pentium4 < %s | FileCheck %s -check-prefix=SSE
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; RUN: llc -march x86 -mcpu pentium3 < %s | FileCheck %s -check-prefix=NOSSE2
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; RUN: llc -march x86 -mcpu pentium2 < %s | FileCheck %s -check-prefix=NOSSE1
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; RUN: llc -march x86 -mcpu pentium < %s | FileCheck %s -check-prefix=NOCMOV
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; PR14035
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define double @test1(i32 %a, i32 %b, double %x) nounwind {
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%cmp = icmp ugt i32 %a, %b
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%sel = select i1 %cmp, double 99.0, double %x
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ret double %sel
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; SSE: test1:
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; SSE: movsd
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; NOSSE2: test1:
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; NOSSE2: fcmovnbe
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; NOSSE1: test1:
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; NOSSE1: fcmovnbe
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; NOCMOV: test1:
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; NOCMOV: fstp
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}
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define double @test2(i32 %a, i32 %b, double %x) nounwind {
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%cmp = icmp uge i32 %a, %b
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%sel = select i1 %cmp, double 99.0, double %x
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ret double %sel
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; SSE: test2:
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; SSE: movsd
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; NOSSE2: test2:
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; NOSSE2: fcmovnb
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; NOSSE1: test2:
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; NOSSE1: fcmovnb
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; NOCMOV: test2:
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; NOCMOV: fstp
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}
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define double @test3(i32 %a, i32 %b, double %x) nounwind {
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%cmp = icmp ult i32 %a, %b
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%sel = select i1 %cmp, double 99.0, double %x
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ret double %sel
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; SSE: test3:
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; SSE: movsd
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; NOSSE2: test3:
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; NOSSE2: fcmovb
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; NOSSE1: test3:
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; NOSSE1: fcmovb
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; NOCMOV: test3:
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; NOCMOV: fstp
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}
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define double @test4(i32 %a, i32 %b, double %x) nounwind {
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%cmp = icmp ule i32 %a, %b
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%sel = select i1 %cmp, double 99.0, double %x
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ret double %sel
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; SSE: test4:
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; SSE: movsd
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; NOSSE2: test4:
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; NOSSE2: fcmovbe
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; NOSSE1: test4:
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; NOSSE1: fcmovbe
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; NOCMOV: test4:
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; NOCMOV: fstp
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}
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define double @test5(i32 %a, i32 %b, double %x) nounwind {
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%cmp = icmp sgt i32 %a, %b
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%sel = select i1 %cmp, double 99.0, double %x
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ret double %sel
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; SSE: test5:
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; SSE: movsd
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; NOSSE2: test5:
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; NOSSE2: fstp
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; NOSSE1: test5:
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; NOSSE1: fstp
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; NOCMOV: test5:
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; NOCMOV: fstp
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}
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define double @test6(i32 %a, i32 %b, double %x) nounwind {
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%cmp = icmp sge i32 %a, %b
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%sel = select i1 %cmp, double 99.0, double %x
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ret double %sel
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; SSE: test6:
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; SSE: movsd
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; NOSSE2: test6:
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; NOSSE2: fstp
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; NOSSE1: test6:
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; NOSSE1: fstp
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; NOCMOV: test6:
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; NOCMOV: fstp
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}
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define double @test7(i32 %a, i32 %b, double %x) nounwind {
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%cmp = icmp slt i32 %a, %b
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%sel = select i1 %cmp, double 99.0, double %x
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ret double %sel
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; SSE: test7:
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; SSE: movsd
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; NOSSE2: test7:
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; NOSSE2: fstp
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; NOSSE1: test7:
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; NOSSE1: fstp
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; NOCMOV: test7:
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; NOCMOV: fstp
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}
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define double @test8(i32 %a, i32 %b, double %x) nounwind {
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%cmp = icmp sle i32 %a, %b
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%sel = select i1 %cmp, double 99.0, double %x
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ret double %sel
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; SSE: test8:
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; SSE: movsd
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; NOSSE2: test8:
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; NOSSE2: fstp
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; NOSSE1: test8:
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; NOSSE1: fstp
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; NOCMOV: test8:
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; NOCMOV: fstp
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}
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define float @test9(i32 %a, i32 %b, float %x) nounwind {
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%cmp = icmp ugt i32 %a, %b
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%sel = select i1 %cmp, float 99.0, float %x
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ret float %sel
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; SSE: test9:
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; SSE: movss
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; NOSSE2: test9:
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; NOSSE2: movss
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; NOSSE1: test9:
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; NOSSE1: fcmovnbe
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; NOCMOV: test9:
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; NOCMOV: fstp
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}
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define float @test10(i32 %a, i32 %b, float %x) nounwind {
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%cmp = icmp uge i32 %a, %b
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%sel = select i1 %cmp, float 99.0, float %x
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ret float %sel
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; SSE: test10:
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; SSE: movss
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; NOSSE2: test10:
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; NOSSE2: movss
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; NOSSE1: test10:
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; NOSSE1: fcmovnb
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; NOCMOV: test10:
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; NOCMOV: fstp
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}
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define float @test11(i32 %a, i32 %b, float %x) nounwind {
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%cmp = icmp ult i32 %a, %b
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%sel = select i1 %cmp, float 99.0, float %x
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ret float %sel
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; SSE: test11:
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; SSE: movss
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; NOSSE2: test11:
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; NOSSE2: movss
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; NOSSE1: test11:
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; NOSSE1: fcmovb
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; NOCMOV: test11:
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; NOCMOV: fstp
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}
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define float @test12(i32 %a, i32 %b, float %x) nounwind {
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%cmp = icmp ule i32 %a, %b
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%sel = select i1 %cmp, float 99.0, float %x
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ret float %sel
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; SSE: test12:
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; SSE: movss
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; NOSSE2: test12:
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; NOSSE2: movss
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; NOSSE1: test12:
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; NOSSE1: fcmovbe
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; NOCMOV: test12:
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; NOCMOV: fstp
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}
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define float @test13(i32 %a, i32 %b, float %x) nounwind {
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%cmp = icmp sgt i32 %a, %b
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%sel = select i1 %cmp, float 99.0, float %x
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ret float %sel
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; SSE: test13:
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; SSE: movss
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; NOSSE2: test13:
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; NOSSE2: movss
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; NOSSE1: test13:
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; NOSSE1: fstp
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; NOCMOV: test13:
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; NOCMOV: fstp
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}
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define float @test14(i32 %a, i32 %b, float %x) nounwind {
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%cmp = icmp sge i32 %a, %b
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%sel = select i1 %cmp, float 99.0, float %x
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ret float %sel
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; SSE: test14:
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; SSE: movss
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; NOSSE2: test14:
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; NOSSE2: movss
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; NOSSE1: test14:
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; NOSSE1: fstp
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; NOCMOV: test14:
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; NOCMOV: fstp
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}
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define float @test15(i32 %a, i32 %b, float %x) nounwind {
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%cmp = icmp slt i32 %a, %b
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%sel = select i1 %cmp, float 99.0, float %x
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ret float %sel
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; SSE: test15:
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; SSE: movss
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; NOSSE2: test15:
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; NOSSE2: movss
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; NOSSE1: test15:
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; NOSSE1: fstp
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; NOCMOV: test15:
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; NOCMOV: fstp
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}
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define float @test16(i32 %a, i32 %b, float %x) nounwind {
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%cmp = icmp sle i32 %a, %b
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%sel = select i1 %cmp, float 99.0, float %x
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ret float %sel
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; SSE: test16:
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; SSE: movss
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; NOSSE2: test16:
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; NOSSE2: movss
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; NOSSE1: test16:
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; NOSSE1: fstp
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; NOCMOV: test16:
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; NOCMOV: fstp
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}
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define x86_fp80 @test17(i32 %a, i32 %b, x86_fp80 %x) nounwind {
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%cmp = icmp ugt i32 %a, %b
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%sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x
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ret x86_fp80 %sel
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; SSE: test17:
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; SSE: fcmovnbe
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; NOSSE2: test17:
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; NOSSE2: fcmovnbe
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; NOSSE1: test17:
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; NOSSE1: fcmovnbe
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; NOCMOV: test17:
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; NOCMOV: fstp
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}
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define x86_fp80 @test18(i32 %a, i32 %b, x86_fp80 %x) nounwind {
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%cmp = icmp uge i32 %a, %b
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%sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x
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ret x86_fp80 %sel
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; SSE: test18:
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; SSE: fcmovnb
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; NOSSE2: test18:
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; NOSSE2: fcmovnb
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; NOSSE1: test18:
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; NOSSE1: fcmovnb
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; NOCMOV: test18:
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; NOCMOV: fstp
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}
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define x86_fp80 @test19(i32 %a, i32 %b, x86_fp80 %x) nounwind {
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%cmp = icmp ult i32 %a, %b
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%sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x
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ret x86_fp80 %sel
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; SSE: test19:
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; SSE: fcmovb
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; NOSSE2: test19:
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; NOSSE2: fcmovb
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; NOSSE1: test19:
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; NOSSE1: fcmovb
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; NOCMOV: test19:
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; NOCMOV: fstp
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}
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define x86_fp80 @test20(i32 %a, i32 %b, x86_fp80 %x) nounwind {
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%cmp = icmp ule i32 %a, %b
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%sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x
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ret x86_fp80 %sel
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; SSE: test20:
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; SSE: fcmovbe
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; NOSSE2: test20:
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; NOSSE2: fcmovbe
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; NOSSE1: test20:
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; NOSSE1: fcmovbe
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; NOCMOV: test20:
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; NOCMOV: fstp
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}
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define x86_fp80 @test21(i32 %a, i32 %b, x86_fp80 %x) nounwind {
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%cmp = icmp sgt i32 %a, %b
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%sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x
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ret x86_fp80 %sel
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; We don't emit a branch for fp80, why?
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; SSE: test21:
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; SSE: testb
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; SSE: fcmovne
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; NOSSE2: test21:
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; NOSSE2: testb
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; NOSSE2: fcmovne
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; NOSSE1: test21:
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; NOSSE1: testb
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; NOSSE1: fcmovne
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; NOCMOV: test21:
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; NOCMOV: fstp
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}
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define x86_fp80 @test22(i32 %a, i32 %b, x86_fp80 %x) nounwind {
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%cmp = icmp sge i32 %a, %b
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%sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x
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ret x86_fp80 %sel
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; SSE: test22:
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; SSE: testb
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; SSE: fcmovne
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; NOSSE2: test22:
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; NOSSE2: testb
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; NOSSE2: fcmovne
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; NOSSE1: test22:
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; NOSSE1: testb
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; NOSSE1: fcmovne
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; NOCMOV: test22:
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; NOCMOV: fstp
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}
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define x86_fp80 @test23(i32 %a, i32 %b, x86_fp80 %x) nounwind {
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%cmp = icmp slt i32 %a, %b
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%sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x
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ret x86_fp80 %sel
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; SSE: test23:
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; SSE: testb
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; SSE: fcmovne
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; NOSSE2: test23:
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; NOSSE2: testb
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; NOSSE2: fcmovne
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; NOSSE1: test23:
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; NOSSE1: testb
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; NOSSE1: fcmovne
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; NOCMOV: test23:
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; NOCMOV: fstp
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}
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define x86_fp80 @test24(i32 %a, i32 %b, x86_fp80 %x) nounwind {
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%cmp = icmp sle i32 %a, %b
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%sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x
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ret x86_fp80 %sel
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; SSE: test24:
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; SSE: testb
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; SSE: fcmovne
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; NOSSE2: test24:
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; NOSSE2: testb
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; NOSSE2: fcmovne
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; NOSSE1: test24:
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; NOSSE1: testb
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; NOSSE1: fcmovne
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; NOCMOV: test24:
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; NOCMOV: fstp
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}
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