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6824f127f9
System z branches have a mask to select which of the 4 CC values should cause the branch to be taken. We can invert a branch by inverting the mask. However, not all instructions can produce all 4 CC values, so inverting the branch like this can lead to some oddities. For example, integer comparisons only produce a CC of 0 (equal), 1 (less) or 2 (greater). If an integer EQ is reversed to NE before instruction selection, the branch will test for 1 or 2. If instead the branch is reversed after instruction selection (by inverting the mask), it will test for 1, 2 or 3. Both are correct, but the second isn't really canonical. This patch therefore keeps track of which CC values are possible and uses this when inverting a mask. Although this is mostly cosmestic, it fixes undefined behavior for the CIJNLH in branch-08.ll. Another fix would have been to mask out bit 0 when generating the fused compare and branch, but the point of this patch is that we shouldn't need to do that in the first place. The patch also makes it easier to reuse CC results from other instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187495 91177308-0d34-0410-b5e6-96231b3b80d8
96 lines
4.4 KiB
TableGen
96 lines
4.4 KiB
TableGen
//===-- SystemZPatterns.td - SystemZ-specific pattern rules ---*- tblgen-*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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// Record that INSN performs a 64-bit version of unary operator OPERATOR
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// in which the operand is sign-extended from 32 to 64 bits.
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multiclass SXU<SDPatternOperator operator, Instruction insn> {
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def : Pat<(operator (sext (i32 GR32:$src))),
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(insn GR32:$src)>;
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def : Pat<(operator (sext_inreg GR64:$src, i32)),
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(insn (EXTRACT_SUBREG GR64:$src, subreg_32bit))>;
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}
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// Record that INSN performs a 64-bit version of binary operator OPERATOR
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// in which the first operand has class CLS and which the second operand
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// is sign-extended from a 32-bit register.
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multiclass SXB<SDPatternOperator operator, RegisterOperand cls,
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Instruction insn> {
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def : Pat<(operator cls:$src1, (sext GR32:$src2)),
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(insn cls:$src1, GR32:$src2)>;
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def : Pat<(operator cls:$src1, (sext_inreg GR64:$src2, i32)),
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(insn cls:$src1, (EXTRACT_SUBREG GR64:$src2, subreg_32bit))>;
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}
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// Like SXB, but for zero extension.
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multiclass ZXB<SDPatternOperator operator, RegisterOperand cls,
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Instruction insn> {
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def : Pat<(operator cls:$src1, (zext GR32:$src2)),
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(insn cls:$src1, GR32:$src2)>;
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def : Pat<(operator cls:$src1, (and GR64:$src2, 0xffffffff)),
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(insn cls:$src1, (EXTRACT_SUBREG GR64:$src2, subreg_32bit))>;
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}
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// Record that INSN performs a binary read-modify-write operation,
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// with LOAD, OPERATOR and STORE being the read, modify and write
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// respectively. MODE is the addressing mode and IMM is the type
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// of the second operand.
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class RMWI<SDPatternOperator load, SDPatternOperator operator,
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SDPatternOperator store, AddressingMode mode,
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PatFrag imm, Instruction insn>
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: Pat<(store (operator (load mode:$addr), imm:$src), mode:$addr),
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(insn mode:$addr, (UIMM8 imm:$src))>;
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// Record that INSN performs binary operation OPERATION on a byte
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// memory location. IMM is the type of the second operand.
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multiclass RMWIByte<SDPatternOperator operator, AddressingMode mode,
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Instruction insn> {
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def : RMWI<anyextloadi8, operator, truncstorei8, mode, imm32, insn>;
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def : RMWI<anyextloadi8, operator, truncstorei8, mode, imm64, insn>;
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}
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// Record that INSN conditionally performs load operation LOAD into a
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// register of class CLS. The load may trap even if the condition is false.
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multiclass CondLoad<Instruction insn, RegisterOperand cls,
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SDPatternOperator load> {
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def : Pat<(z_select_ccmask (load bdaddr20only:$addr), cls:$new, uimm8zx4,
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uimm8zx4:$cc),
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(insn cls:$new, bdaddr20only:$addr, uimm8zx4:$cc)>,
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Requires<[FeatureLoadStoreOnCond]>;
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def : Pat<(z_select_ccmask cls:$new, (load bdaddr20only:$addr), uimm8zx4,
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uimm8zx4:$cc),
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(insn cls:$new, bdaddr20only:$addr, (INVCC uimm8zx4:$cc))>,
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Requires<[FeatureLoadStoreOnCond]>;
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}
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// Record that INSN performs insertion TYPE into a register of class CLS.
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// The inserted operand is loaded using LOAD from an address of mode MODE.
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multiclass InsertMem<string type, Instruction insn, RegisterOperand cls,
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SDPatternOperator load, AddressingMode mode> {
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def : Pat<(!cast<SDPatternOperator>("or_as_"##type)
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cls:$src1, (load mode:$src2)),
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(insn cls:$src1, mode:$src2)>;
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def : Pat<(!cast<SDPatternOperator>("or_as_rev"##type)
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(load mode:$src2), cls:$src1),
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(insn cls:$src1, mode:$src2)>;
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}
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// Use MVC instruction INSN for a load of type LOAD followed by a store
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// of type STORE. VT is the type of the intermediate register and LENGTH
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// is the number of bytes to copy (which may be smaller than VT).
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multiclass MVCLoadStore<SDPatternOperator load, SDPatternOperator store,
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ValueType vt, Instruction insn, bits<5> length> {
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def Pat : PatFrag<(ops node:$dest, node:$src),
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(store (vt (load node:$src)), node:$dest),
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[{ return storeLoadCanUseMVC(N); }]>;
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def : Pat<(!cast<SDPatternOperator>(NAME##"Pat") bdaddr12only:$dest,
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bdaddr12only:$src),
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(insn bdaddr12only:$dest, bdaddr12only:$src, length)>;
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}
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