llvm-6502/test/CodeGen
Quentin Colombet 685b0d9315 Lower unsigned vsetcc to psubus in certain cases
The current approach to lower a vsetult is to flip the sign bit of the
operands, swap the operands and then use a (signed) pcmpgt.  psubus (unsigned
saturating subtract) can be used to emulate a vsetult more efficiently:

+    case ISD::SETULT: {
+      // If the comparison is against a constant we can turn this into a
+      // setule.  With psubus, setule does not require a swap.  This is
+      // beneficial because the constant in the register is no longer
+      // destructed as the destination so it can be hoisted out of a loop.

I also enable lowering via psubus in a few other cases where it's clearly
beneficial: setule and setuge if minu/maxu cannot be used.
    
rdar://problem/14338765

Patch by Adam Nemet <anemet@apple.com>.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202301 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-26 21:39:12 +00:00
..
AArch64 AArch64: simplify tbl/tbx polymorphism 2014-02-26 11:55:09 +00:00
ARM Stop test/CodeGen/ARM/a15.ll targetting non-ARM targets. 2014-02-26 11:26:18 +00:00
CPP
Generic
Hexagon
Inputs
Mips
MSP430
NVPTX
PowerPC Account for 128-bit integer operations in PPCCTRLoops 2014-02-25 20:51:50 +00:00
R600 R600/SI: Custom select 64-bit ADD 2014-02-25 21:36:18 +00:00
SPARC SPARC: Implement TRAP lowering. Matches what GCC emits. 2014-02-23 21:43:52 +00:00
SystemZ
Thumb
Thumb2 ARMv8 IfConversion must skip narrow instructions that a) define CPSR and b) wouldn't affect CPSR in an IT block 2014-02-26 11:27:28 +00:00
X86 Lower unsigned vsetcc to psubus in certain cases 2014-02-26 21:39:12 +00:00
XCore [XCore] Add intrinsic for CLRPT (clear port time) instruction. 2014-02-25 17:31:15 +00:00