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TableGen had diagnostic printers sprinkled about in a few places. Pull them together into a single location in Error.cpp. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133568 91177308-0d34-0410-b5e6-96231b3b80d8
620 lines
23 KiB
C++
620 lines
23 KiB
C++
//===- CodeGenRegisters.cpp - Register and RegisterClass Info -------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines structures to encapsulate information gleaned from the
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// target register and register class definitions.
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//
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//===----------------------------------------------------------------------===//
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#include "CodeGenRegisters.h"
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#include "CodeGenTarget.h"
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#include "Error.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/StringExtras.h"
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using namespace llvm;
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//===----------------------------------------------------------------------===//
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// CodeGenRegister
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//===----------------------------------------------------------------------===//
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CodeGenRegister::CodeGenRegister(Record *R, unsigned Enum)
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: TheDef(R),
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EnumValue(Enum),
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CostPerUse(R->getValueAsInt("CostPerUse")),
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SubRegsComplete(false)
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{}
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const std::string &CodeGenRegister::getName() const {
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return TheDef->getName();
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}
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namespace {
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struct Orphan {
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CodeGenRegister *SubReg;
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Record *First, *Second;
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Orphan(CodeGenRegister *r, Record *a, Record *b)
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: SubReg(r), First(a), Second(b) {}
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};
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}
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const CodeGenRegister::SubRegMap &
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CodeGenRegister::getSubRegs(CodeGenRegBank &RegBank) {
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// Only compute this map once.
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if (SubRegsComplete)
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return SubRegs;
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SubRegsComplete = true;
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std::vector<Record*> SubList = TheDef->getValueAsListOfDefs("SubRegs");
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std::vector<Record*> Indices = TheDef->getValueAsListOfDefs("SubRegIndices");
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if (SubList.size() != Indices.size())
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throw TGError(TheDef->getLoc(), "Register " + getName() +
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" SubRegIndices doesn't match SubRegs");
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// First insert the direct subregs and make sure they are fully indexed.
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for (unsigned i = 0, e = SubList.size(); i != e; ++i) {
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CodeGenRegister *SR = RegBank.getReg(SubList[i]);
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if (!SubRegs.insert(std::make_pair(Indices[i], SR)).second)
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throw TGError(TheDef->getLoc(), "SubRegIndex " + Indices[i]->getName() +
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" appears twice in Register " + getName());
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}
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// Keep track of inherited subregs and how they can be reached.
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SmallVector<Orphan, 8> Orphans;
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// Clone inherited subregs and place duplicate entries on Orphans.
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// Here the order is important - earlier subregs take precedence.
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for (unsigned i = 0, e = SubList.size(); i != e; ++i) {
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CodeGenRegister *SR = RegBank.getReg(SubList[i]);
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const SubRegMap &Map = SR->getSubRegs(RegBank);
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// Add this as a super-register of SR now all sub-registers are in the list.
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// This creates a topological ordering, the exact order depends on the
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// order getSubRegs is called on all registers.
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SR->SuperRegs.push_back(this);
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for (SubRegMap::const_iterator SI = Map.begin(), SE = Map.end(); SI != SE;
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++SI) {
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if (!SubRegs.insert(*SI).second)
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Orphans.push_back(Orphan(SI->second, Indices[i], SI->first));
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// Noop sub-register indexes are possible, so avoid duplicates.
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if (SI->second != SR)
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SI->second->SuperRegs.push_back(this);
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}
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}
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// Process the composites.
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ListInit *Comps = TheDef->getValueAsListInit("CompositeIndices");
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for (unsigned i = 0, e = Comps->size(); i != e; ++i) {
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DagInit *Pat = dynamic_cast<DagInit*>(Comps->getElement(i));
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if (!Pat)
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throw TGError(TheDef->getLoc(), "Invalid dag '" +
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Comps->getElement(i)->getAsString() +
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"' in CompositeIndices");
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DefInit *BaseIdxInit = dynamic_cast<DefInit*>(Pat->getOperator());
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if (!BaseIdxInit || !BaseIdxInit->getDef()->isSubClassOf("SubRegIndex"))
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throw TGError(TheDef->getLoc(), "Invalid SubClassIndex in " +
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Pat->getAsString());
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// Resolve list of subreg indices into R2.
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CodeGenRegister *R2 = this;
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for (DagInit::const_arg_iterator di = Pat->arg_begin(),
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de = Pat->arg_end(); di != de; ++di) {
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DefInit *IdxInit = dynamic_cast<DefInit*>(*di);
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if (!IdxInit || !IdxInit->getDef()->isSubClassOf("SubRegIndex"))
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throw TGError(TheDef->getLoc(), "Invalid SubClassIndex in " +
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Pat->getAsString());
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const SubRegMap &R2Subs = R2->getSubRegs(RegBank);
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SubRegMap::const_iterator ni = R2Subs.find(IdxInit->getDef());
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if (ni == R2Subs.end())
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throw TGError(TheDef->getLoc(), "Composite " + Pat->getAsString() +
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" refers to bad index in " + R2->getName());
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R2 = ni->second;
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}
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// Insert composite index. Allow overriding inherited indices etc.
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SubRegs[BaseIdxInit->getDef()] = R2;
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// R2 is no longer an orphan.
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for (unsigned j = 0, je = Orphans.size(); j != je; ++j)
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if (Orphans[j].SubReg == R2)
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Orphans[j].SubReg = 0;
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}
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// Now Orphans contains the inherited subregisters without a direct index.
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// Create inferred indexes for all missing entries.
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for (unsigned i = 0, e = Orphans.size(); i != e; ++i) {
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Orphan &O = Orphans[i];
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if (!O.SubReg)
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continue;
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SubRegs[RegBank.getCompositeSubRegIndex(O.First, O.Second, true)] =
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O.SubReg;
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}
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return SubRegs;
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}
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void
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CodeGenRegister::addSubRegsPreOrder(SetVector<CodeGenRegister*> &OSet) const {
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assert(SubRegsComplete && "Must precompute sub-registers");
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std::vector<Record*> Indices = TheDef->getValueAsListOfDefs("SubRegIndices");
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for (unsigned i = 0, e = Indices.size(); i != e; ++i) {
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CodeGenRegister *SR = SubRegs.find(Indices[i])->second;
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if (OSet.insert(SR))
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SR->addSubRegsPreOrder(OSet);
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}
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}
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//===----------------------------------------------------------------------===//
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// RegisterTuples
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//===----------------------------------------------------------------------===//
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// A RegisterTuples def is used to generate pseudo-registers from lists of
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// sub-registers. We provide a SetTheory expander class that returns the new
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// registers.
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namespace {
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struct TupleExpander : SetTheory::Expander {
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void expand(SetTheory &ST, Record *Def, SetTheory::RecSet &Elts) {
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std::vector<Record*> Indices = Def->getValueAsListOfDefs("SubRegIndices");
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unsigned Dim = Indices.size();
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ListInit *SubRegs = Def->getValueAsListInit("SubRegs");
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if (Dim != SubRegs->getSize())
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throw TGError(Def->getLoc(), "SubRegIndices and SubRegs size mismatch");
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if (Dim < 2)
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throw TGError(Def->getLoc(), "Tuples must have at least 2 sub-registers");
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// Evaluate the sub-register lists to be zipped.
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unsigned Length = ~0u;
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SmallVector<SetTheory::RecSet, 4> Lists(Dim);
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for (unsigned i = 0; i != Dim; ++i) {
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ST.evaluate(SubRegs->getElement(i), Lists[i]);
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Length = std::min(Length, unsigned(Lists[i].size()));
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}
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if (Length == 0)
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return;
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// Precompute some types.
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Record *RegisterCl = Def->getRecords().getClass("Register");
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RecTy *RegisterRecTy = new RecordRecTy(RegisterCl);
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StringInit *BlankName = new StringInit("");
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// Zip them up.
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for (unsigned n = 0; n != Length; ++n) {
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std::string Name;
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Record *Proto = Lists[0][n];
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std::vector<Init*> Tuple;
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unsigned CostPerUse = 0;
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for (unsigned i = 0; i != Dim; ++i) {
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Record *Reg = Lists[i][n];
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if (i) Name += '_';
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Name += Reg->getName();
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Tuple.push_back(new DefInit(Reg));
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CostPerUse = std::max(CostPerUse,
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unsigned(Reg->getValueAsInt("CostPerUse")));
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}
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// Create a new Record representing the synthesized register. This record
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// is only for consumption by CodeGenRegister, it is not added to the
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// RecordKeeper.
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Record *NewReg = new Record(Name, Def->getLoc(), Def->getRecords());
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Elts.insert(NewReg);
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// Copy Proto super-classes.
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for (unsigned i = 0, e = Proto->getSuperClasses().size(); i != e; ++i)
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NewReg->addSuperClass(Proto->getSuperClasses()[i]);
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// Copy Proto fields.
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for (unsigned i = 0, e = Proto->getValues().size(); i != e; ++i) {
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RecordVal RV = Proto->getValues()[i];
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// Replace the sub-register list with Tuple.
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if (RV.getName() == "SubRegs")
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RV.setValue(new ListInit(Tuple, RegisterRecTy));
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// Provide a blank AsmName. MC hacks are required anyway.
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if (RV.getName() == "AsmName")
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RV.setValue(BlankName);
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// CostPerUse is aggregated from all Tuple members.
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if (RV.getName() == "CostPerUse")
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RV.setValue(new IntInit(CostPerUse));
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// Copy fields from the RegisterTuples def.
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if (RV.getName() == "SubRegIndices" ||
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RV.getName() == "CompositeIndices") {
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NewReg->addValue(*Def->getValue(RV.getName()));
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continue;
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}
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// Some fields get their default uninitialized value.
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if (RV.getName() == "DwarfNumbers" ||
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RV.getName() == "DwarfAlias" ||
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RV.getName() == "Aliases") {
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if (const RecordVal *DefRV = RegisterCl->getValue(RV.getName()))
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NewReg->addValue(*DefRV);
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continue;
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}
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// Everything else is copied from Proto.
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NewReg->addValue(RV);
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}
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}
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}
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};
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}
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//===----------------------------------------------------------------------===//
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// CodeGenRegisterClass
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//===----------------------------------------------------------------------===//
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CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank, Record *R)
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: TheDef(R) {
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// Rename anonymous register classes.
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if (R->getName().size() > 9 && R->getName()[9] == '.') {
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static unsigned AnonCounter = 0;
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R->setName("AnonRegClass_"+utostr(AnonCounter++));
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}
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std::vector<Record*> TypeList = R->getValueAsListOfDefs("RegTypes");
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for (unsigned i = 0, e = TypeList.size(); i != e; ++i) {
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Record *Type = TypeList[i];
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if (!Type->isSubClassOf("ValueType"))
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throw "RegTypes list member '" + Type->getName() +
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"' does not derive from the ValueType class!";
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VTs.push_back(getValueType(Type));
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}
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assert(!VTs.empty() && "RegisterClass must contain at least one ValueType!");
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// Default allocation order always contains all registers.
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Elements = RegBank.getSets().expand(R);
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for (unsigned i = 0, e = Elements->size(); i != e; ++i)
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Members.insert(RegBank.getReg((*Elements)[i]));
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// Alternative allocation orders may be subsets.
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ListInit *Alts = R->getValueAsListInit("AltOrders");
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AltOrders.resize(Alts->size());
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SetTheory::RecSet Order;
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for (unsigned i = 0, e = Alts->size(); i != e; ++i) {
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RegBank.getSets().evaluate(Alts->getElement(i), Order);
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AltOrders[i].append(Order.begin(), Order.end());
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// Verify that all altorder members are regclass members.
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while (!Order.empty()) {
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CodeGenRegister *Reg = RegBank.getReg(Order.back());
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Order.pop_back();
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if (!contains(Reg))
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throw TGError(R->getLoc(), " AltOrder register " + Reg->getName() +
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" is not a class member");
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}
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}
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// SubRegClasses is a list<dag> containing (RC, subregindex, ...) dags.
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ListInit *SRC = R->getValueAsListInit("SubRegClasses");
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for (ListInit::const_iterator i = SRC->begin(), e = SRC->end(); i != e; ++i) {
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DagInit *DAG = dynamic_cast<DagInit*>(*i);
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if (!DAG) throw "SubRegClasses must contain DAGs";
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DefInit *DAGOp = dynamic_cast<DefInit*>(DAG->getOperator());
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Record *RCRec;
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if (!DAGOp || !(RCRec = DAGOp->getDef())->isSubClassOf("RegisterClass"))
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throw "Operator '" + DAG->getOperator()->getAsString() +
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"' in SubRegClasses is not a RegisterClass";
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// Iterate over args, all SubRegIndex instances.
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for (DagInit::const_arg_iterator ai = DAG->arg_begin(), ae = DAG->arg_end();
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ai != ae; ++ai) {
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DefInit *Idx = dynamic_cast<DefInit*>(*ai);
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Record *IdxRec;
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if (!Idx || !(IdxRec = Idx->getDef())->isSubClassOf("SubRegIndex"))
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throw "Argument '" + (*ai)->getAsString() +
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"' in SubRegClasses is not a SubRegIndex";
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if (!SubRegClasses.insert(std::make_pair(IdxRec, RCRec)).second)
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throw "SubRegIndex '" + IdxRec->getName() + "' mentioned twice";
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}
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}
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// Allow targets to override the size in bits of the RegisterClass.
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unsigned Size = R->getValueAsInt("Size");
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Namespace = R->getValueAsString("Namespace");
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SpillSize = Size ? Size : EVT(VTs[0]).getSizeInBits();
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SpillAlignment = R->getValueAsInt("Alignment");
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CopyCost = R->getValueAsInt("CopyCost");
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Allocatable = R->getValueAsBit("isAllocatable");
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AltOrderSelect = R->getValueAsCode("AltOrderSelect");
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}
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bool CodeGenRegisterClass::contains(const CodeGenRegister *Reg) const {
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return Members.count(Reg);
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}
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// Returns true if RC is a strict subclass.
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// RC is a sub-class of this class if it is a valid replacement for any
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// instruction operand where a register of this classis required. It must
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// satisfy these conditions:
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//
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// 1. All RC registers are also in this.
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// 2. The RC spill size must not be smaller than our spill size.
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// 3. RC spill alignment must be compatible with ours.
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//
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bool CodeGenRegisterClass::hasSubClass(const CodeGenRegisterClass *RC) const {
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return SpillAlignment && RC->SpillAlignment % SpillAlignment == 0 &&
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SpillSize <= RC->SpillSize &&
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std::includes(Members.begin(), Members.end(),
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RC->Members.begin(), RC->Members.end(),
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CodeGenRegister::Less());
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}
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const std::string &CodeGenRegisterClass::getName() const {
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return TheDef->getName();
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}
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//===----------------------------------------------------------------------===//
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// CodeGenRegBank
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//===----------------------------------------------------------------------===//
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CodeGenRegBank::CodeGenRegBank(RecordKeeper &Records) : Records(Records) {
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// Configure register Sets to understand register classes and tuples.
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Sets.addFieldExpander("RegisterClass", "MemberList");
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Sets.addExpander("RegisterTuples", new TupleExpander());
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// Read in the user-defined (named) sub-register indices.
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// More indices will be synthesized later.
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SubRegIndices = Records.getAllDerivedDefinitions("SubRegIndex");
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std::sort(SubRegIndices.begin(), SubRegIndices.end(), LessRecord());
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NumNamedIndices = SubRegIndices.size();
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// Read in the register definitions.
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std::vector<Record*> Regs = Records.getAllDerivedDefinitions("Register");
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std::sort(Regs.begin(), Regs.end(), LessRecord());
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Registers.reserve(Regs.size());
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// Assign the enumeration values.
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for (unsigned i = 0, e = Regs.size(); i != e; ++i)
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getReg(Regs[i]);
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// Expand tuples and number the new registers.
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std::vector<Record*> Tups =
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Records.getAllDerivedDefinitions("RegisterTuples");
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for (unsigned i = 0, e = Tups.size(); i != e; ++i) {
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const std::vector<Record*> *TupRegs = Sets.expand(Tups[i]);
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for (unsigned j = 0, je = TupRegs->size(); j != je; ++j)
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getReg((*TupRegs)[j]);
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}
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// Read in register class definitions.
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std::vector<Record*> RCs = Records.getAllDerivedDefinitions("RegisterClass");
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if (RCs.empty())
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throw std::string("No 'RegisterClass' subclasses defined!");
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RegClasses.reserve(RCs.size());
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for (unsigned i = 0, e = RCs.size(); i != e; ++i)
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RegClasses.push_back(CodeGenRegisterClass(*this, RCs[i]));
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}
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CodeGenRegister *CodeGenRegBank::getReg(Record *Def) {
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CodeGenRegister *&Reg = Def2Reg[Def];
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if (Reg)
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return Reg;
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Reg = new CodeGenRegister(Def, Registers.size() + 1);
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Registers.push_back(Reg);
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return Reg;
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}
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CodeGenRegisterClass *CodeGenRegBank::getRegClass(Record *Def) {
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if (Def2RC.empty())
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for (unsigned i = 0, e = RegClasses.size(); i != e; ++i)
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Def2RC[RegClasses[i].TheDef] = &RegClasses[i];
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if (CodeGenRegisterClass *RC = Def2RC[Def])
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return RC;
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throw TGError(Def->getLoc(), "Not a known RegisterClass!");
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}
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Record *CodeGenRegBank::getCompositeSubRegIndex(Record *A, Record *B,
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bool create) {
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// Look for an existing entry.
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Record *&Comp = Composite[std::make_pair(A, B)];
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if (Comp || !create)
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return Comp;
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// None exists, synthesize one.
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std::string Name = A->getName() + "_then_" + B->getName();
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Comp = new Record(Name, SMLoc(), Records);
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Records.addDef(Comp);
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SubRegIndices.push_back(Comp);
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return Comp;
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}
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unsigned CodeGenRegBank::getSubRegIndexNo(Record *idx) {
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std::vector<Record*>::const_iterator i =
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std::find(SubRegIndices.begin(), SubRegIndices.end(), idx);
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assert(i != SubRegIndices.end() && "Not a SubRegIndex");
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return (i - SubRegIndices.begin()) + 1;
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}
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void CodeGenRegBank::computeComposites() {
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// Precompute all sub-register maps. This will create Composite entries for
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// all inferred sub-register indices.
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for (unsigned i = 0, e = Registers.size(); i != e; ++i)
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Registers[i]->getSubRegs(*this);
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for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
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CodeGenRegister *Reg1 = Registers[i];
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const CodeGenRegister::SubRegMap &SRM1 = Reg1->getSubRegs();
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for (CodeGenRegister::SubRegMap::const_iterator i1 = SRM1.begin(),
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e1 = SRM1.end(); i1 != e1; ++i1) {
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Record *Idx1 = i1->first;
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CodeGenRegister *Reg2 = i1->second;
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// Ignore identity compositions.
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if (Reg1 == Reg2)
|
|
continue;
|
|
const CodeGenRegister::SubRegMap &SRM2 = Reg2->getSubRegs();
|
|
// Try composing Idx1 with another SubRegIndex.
|
|
for (CodeGenRegister::SubRegMap::const_iterator i2 = SRM2.begin(),
|
|
e2 = SRM2.end(); i2 != e2; ++i2) {
|
|
std::pair<Record*, Record*> IdxPair(Idx1, i2->first);
|
|
CodeGenRegister *Reg3 = i2->second;
|
|
// Ignore identity compositions.
|
|
if (Reg2 == Reg3)
|
|
continue;
|
|
// OK Reg1:IdxPair == Reg3. Find the index with Reg:Idx == Reg3.
|
|
for (CodeGenRegister::SubRegMap::const_iterator i1d = SRM1.begin(),
|
|
e1d = SRM1.end(); i1d != e1d; ++i1d) {
|
|
if (i1d->second == Reg3) {
|
|
std::pair<CompositeMap::iterator, bool> Ins =
|
|
Composite.insert(std::make_pair(IdxPair, i1d->first));
|
|
// Conflicting composition? Emit a warning but allow it.
|
|
if (!Ins.second && Ins.first->second != i1d->first) {
|
|
errs() << "Warning: SubRegIndex " << getQualifiedName(Idx1)
|
|
<< " and " << getQualifiedName(IdxPair.second)
|
|
<< " compose ambiguously as "
|
|
<< getQualifiedName(Ins.first->second) << " or "
|
|
<< getQualifiedName(i1d->first) << "\n";
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
// We don't care about the difference between (Idx1, Idx2) -> Idx2 and invalid
|
|
// compositions, so remove any mappings of that form.
|
|
for (CompositeMap::iterator i = Composite.begin(), e = Composite.end();
|
|
i != e;) {
|
|
CompositeMap::iterator j = i;
|
|
++i;
|
|
if (j->first.second == j->second)
|
|
Composite.erase(j);
|
|
}
|
|
}
|
|
|
|
// Compute sets of overlapping registers.
|
|
//
|
|
// The standard set is all super-registers and all sub-registers, but the
|
|
// target description can add arbitrary overlapping registers via the 'Aliases'
|
|
// field. This complicates things, but we can compute overlapping sets using
|
|
// the following rules:
|
|
//
|
|
// 1. The relation overlap(A, B) is reflexive and symmetric but not transitive.
|
|
//
|
|
// 2. overlap(A, B) implies overlap(A, S) for all S in supers(B).
|
|
//
|
|
// Alternatively:
|
|
//
|
|
// overlap(A, B) iff there exists:
|
|
// A' in { A, subregs(A) } and B' in { B, subregs(B) } such that:
|
|
// A' = B' or A' in aliases(B') or B' in aliases(A').
|
|
//
|
|
// Here subregs(A) is the full flattened sub-register set returned by
|
|
// A.getSubRegs() while aliases(A) is simply the special 'Aliases' field in the
|
|
// description of register A.
|
|
//
|
|
// This also implies that registers with a common sub-register are considered
|
|
// overlapping. This can happen when forming register pairs:
|
|
//
|
|
// P0 = (R0, R1)
|
|
// P1 = (R1, R2)
|
|
// P2 = (R2, R3)
|
|
//
|
|
// In this case, we will infer an overlap between P0 and P1 because of the
|
|
// shared sub-register R1. There is no overlap between P0 and P2.
|
|
//
|
|
void CodeGenRegBank::
|
|
computeOverlaps(std::map<const CodeGenRegister*, CodeGenRegister::Set> &Map) {
|
|
assert(Map.empty());
|
|
|
|
// Collect overlaps that don't follow from rule 2.
|
|
for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
|
|
CodeGenRegister *Reg = Registers[i];
|
|
CodeGenRegister::Set &Overlaps = Map[Reg];
|
|
|
|
// Reg overlaps itself.
|
|
Overlaps.insert(Reg);
|
|
|
|
// All super-registers overlap.
|
|
const CodeGenRegister::SuperRegList &Supers = Reg->getSuperRegs();
|
|
Overlaps.insert(Supers.begin(), Supers.end());
|
|
|
|
// Form symmetrical relations from the special Aliases[] lists.
|
|
std::vector<Record*> RegList = Reg->TheDef->getValueAsListOfDefs("Aliases");
|
|
for (unsigned i2 = 0, e2 = RegList.size(); i2 != e2; ++i2) {
|
|
CodeGenRegister *Reg2 = getReg(RegList[i2]);
|
|
CodeGenRegister::Set &Overlaps2 = Map[Reg2];
|
|
const CodeGenRegister::SuperRegList &Supers2 = Reg2->getSuperRegs();
|
|
// Reg overlaps Reg2 which implies it overlaps supers(Reg2).
|
|
Overlaps.insert(Reg2);
|
|
Overlaps.insert(Supers2.begin(), Supers2.end());
|
|
Overlaps2.insert(Reg);
|
|
Overlaps2.insert(Supers.begin(), Supers.end());
|
|
}
|
|
}
|
|
|
|
// Apply rule 2. and inherit all sub-register overlaps.
|
|
for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
|
|
CodeGenRegister *Reg = Registers[i];
|
|
CodeGenRegister::Set &Overlaps = Map[Reg];
|
|
const CodeGenRegister::SubRegMap &SRM = Reg->getSubRegs();
|
|
for (CodeGenRegister::SubRegMap::const_iterator i2 = SRM.begin(),
|
|
e2 = SRM.end(); i2 != e2; ++i2) {
|
|
CodeGenRegister::Set &Overlaps2 = Map[i2->second];
|
|
Overlaps.insert(Overlaps2.begin(), Overlaps2.end());
|
|
}
|
|
}
|
|
}
|
|
|
|
void CodeGenRegBank::computeDerivedInfo() {
|
|
computeComposites();
|
|
}
|
|
|
|
/// getRegisterClassForRegister - Find the register class that contains the
|
|
/// specified physical register. If the register is not in a register class,
|
|
/// return null. If the register is in multiple classes, and the classes have a
|
|
/// superset-subset relationship and the same set of types, return the
|
|
/// superclass. Otherwise return null.
|
|
const CodeGenRegisterClass*
|
|
CodeGenRegBank::getRegClassForRegister(Record *R) {
|
|
const CodeGenRegister *Reg = getReg(R);
|
|
const std::vector<CodeGenRegisterClass> &RCs = getRegClasses();
|
|
const CodeGenRegisterClass *FoundRC = 0;
|
|
for (unsigned i = 0, e = RCs.size(); i != e; ++i) {
|
|
const CodeGenRegisterClass &RC = RCs[i];
|
|
if (!RC.contains(Reg))
|
|
continue;
|
|
|
|
// If this is the first class that contains the register,
|
|
// make a note of it and go on to the next class.
|
|
if (!FoundRC) {
|
|
FoundRC = &RC;
|
|
continue;
|
|
}
|
|
|
|
// If a register's classes have different types, return null.
|
|
if (RC.getValueTypes() != FoundRC->getValueTypes())
|
|
return 0;
|
|
|
|
// Check to see if the previously found class that contains
|
|
// the register is a subclass of the current class. If so,
|
|
// prefer the superclass.
|
|
if (RC.hasSubClass(FoundRC)) {
|
|
FoundRC = &RC;
|
|
continue;
|
|
}
|
|
|
|
// Check to see if the previously found class that contains
|
|
// the register is a superclass of the current class. If so,
|
|
// prefer the superclass.
|
|
if (FoundRC->hasSubClass(&RC))
|
|
continue;
|
|
|
|
// Multiple classes, and neither is a superclass of the other.
|
|
// Return null.
|
|
return 0;
|
|
}
|
|
return FoundRC;
|
|
}
|