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https://github.com/c64scene-ar/llvm-6502.git
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7b837d8c75
This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
96 lines
3.3 KiB
TableGen
96 lines
3.3 KiB
TableGen
//===- ARM64.td - Describe the ARM64 Target Machine --------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Target-independent interfaces which we are implementing
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//===----------------------------------------------------------------------===//
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include "llvm/Target/Target.td"
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//===----------------------------------------------------------------------===//
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// ARM64 Subtarget features.
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//
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/// Cyclone has register move instructions which are "free".
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def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true",
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"Has zereo-cycle register moves">;
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/// Cyclone has instructions which zero registers for "free".
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def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
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"Has zero-cycle zeroing instructions">;
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//===----------------------------------------------------------------------===//
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// Register File Description
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//===----------------------------------------------------------------------===//
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include "ARM64RegisterInfo.td"
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include "ARM64CallingConvention.td"
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//===----------------------------------------------------------------------===//
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// Instruction Descriptions
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//===----------------------------------------------------------------------===//
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include "ARM64Schedule.td"
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include "ARM64InstrInfo.td"
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def ARM64InstrInfo : InstrInfo;
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//===----------------------------------------------------------------------===//
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// ARM64 Processors supported.
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//
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include "ARM64SchedCyclone.td"
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def : ProcessorModel<"arm64-generic", NoSchedModel, []>;
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def : ProcessorModel<"cyclone", CycloneModel, [FeatureZCRegMove, FeatureZCZeroing]>;
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//===----------------------------------------------------------------------===//
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// Assembly parser
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//===----------------------------------------------------------------------===//
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def GenericAsmParserVariant : AsmParserVariant {
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int Variant = 0;
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string Name = "generic";
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}
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def AppleAsmParserVariant : AsmParserVariant {
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int Variant = 1;
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string Name = "apple-neon";
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}
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//===----------------------------------------------------------------------===//
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// Assembly printer
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//===----------------------------------------------------------------------===//
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// ARM64 Uses the MC printer for asm output, so make sure the TableGen
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// AsmWriter bits get associated with the correct class.
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def GenericAsmWriter : AsmWriter {
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string AsmWriterClassName = "InstPrinter";
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int Variant = 0;
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bit isMCAsmWriter = 1;
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}
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def AppleAsmWriter : AsmWriter {
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let AsmWriterClassName = "AppleInstPrinter";
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int Variant = 1;
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int isMCAsmWriter = 1;
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}
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//===----------------------------------------------------------------------===//
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// Target Declaration
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//===----------------------------------------------------------------------===//
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def ARM64 : Target {
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let InstructionSet = ARM64InstrInfo;
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let AssemblyParserVariants = [GenericAsmParserVariant, AppleAsmParserVariant];
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let AssemblyWriters = [GenericAsmWriter, AppleAsmWriter];
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}
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