Sanjay Patel 6902c687b0 Optimize vector fabs of bitcasted constant integer values. ... Allow vector fabs operations on bitcasted constant integer values to be optimized in the same way that we already optimize scalar fabs. So for code like this: %bitcast = bitcast i64 18446744069414584320 to <2 x float> ; 0xFFFF_FFFF_0000_0000 %fabs = call <2 x float> @llvm.fabs.v2f32(<2 x float> %bitcast) %ret = bitcast <2 x float> %fabs to i64 Instead of generating something like this: movabsq (constant pool loadi of mask for sign bits) vmovq (move from integer register to vector/fp register) vandps (mask off sign bits) vmovq (move vector/fp register back to integer return register) We should generate: mov (put constant value in return register) I have also removed a redundant clause in the first 'if' statement: N0.getOperand(0).getValueType().isInteger() is the same thing as: IntVT.isInteger() Testcases for x86 and ARM added to existing files that deal with vector fabs. One existing testcase for x86 removed because it is no longer ideal. For more background, please see: http://reviews.llvm.org/D4770 And: http://llvm.org/bugs/show_bug.cgi?id=20354 Differential Revision: http://reviews.llvm.org/D4785 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214892 91177308-0d34-0410-b5e6-96231b3b80d8		2014-08-05 17:35:22 +00:00
..
AArch64	AArch64: Add support for instruction prefetch intrinsic	2014-08-05 12:46:47 +00:00
ARM	Optimize vector fabs of bitcasted constant integer values.	2014-08-05 17:35:22 +00:00
CPP	IR: add "cmpxchg weak" variant to support permitted failure.	2014-06-13 14:24:07 +00:00
Generic	Use "weak alias" instead of "alias weak"	2014-07-30 22:51:54 +00:00
Hexagon	Reduce verbiage of lit.local.cfg files	2014-06-09 22:42:55 +00:00
Inputs
Mips	llvm/test/CodeGen/Mips/cconv/arguments-varargs.ll: Add explicit -mtriple=(mips|mipsel)-linux on 4 lines.	2014-08-01 22:15:38 +00:00
MSP430	Reduce verbiage of lit.local.cfg files	2014-06-09 22:42:55 +00:00
NVPTX	[NVPTX] Add some extra tests for mul.wide to test non-power-of-two source types	2014-07-23 20:23:49 +00:00
PowerPC	[PPC64LE] Fix wrong IR for vec_sld and vec_vsldoi	2014-08-04 23:21:01 +00:00
R600	R600/SI: Update MUBUF assembly string to match AMD proprietary compiler	2014-08-05 14:48:12 +00:00
SPARC	IR: add "cmpxchg weak" variant to support permitted failure.	2014-06-13 14:24:07 +00:00
SystemZ	IR: add "cmpxchg weak" variant to support permitted failure.	2014-06-13 14:24:07 +00:00
Thumb	[ARM] In dynamic-no-pic mode, ARM's post-RA pseudo expansion was incorrectly	2014-08-02 05:40:40 +00:00
Thumb2	[ARM] In dynamic-no-pic mode, ARM's post-RA pseudo expansion was incorrectly	2014-08-02 05:40:40 +00:00
X86	Optimize vector fabs of bitcasted constant integer values.	2014-08-05 17:35:22 +00:00
XCore	llvm/test/CodeGen/XCore/dwarf_debug.ll: Fix not to be affected by *-win32.	2014-07-04 11:58:03 +00:00