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ce7f347da2
a pre-splitting pass over loads and stores. Historically, splitting could cause enough problems that I hamstrung the entire process with a requirement that splittable integer loads and stores must cover the entire alloca. All smaller loads and stores were unsplittable to prevent chaos from ensuing. With the new pre-splitting logic that does load/store pair splitting I introduced in r225061, we can now very nicely handle arbitrarily splittable loads and stores. In order to fully benefit from these smarts, we need to mark all of the integer loads and stores as splittable. However, we don't actually want to rewrite partitions with all integer loads and stores marked as splittable. This will fail to extract scalar integers from aggregates, which is kind of the point of SROA. =] In order to resolve this, what we really want to do is only do pre-splitting on the alloca slices with integer loads and stores fully splittable. This allows us to uncover all non-integer uses of the alloca that would benefit from a split in an integer load or store (and where introducing the split is safe because it is just memory transfer from a load to a store). Once done, we make all the non-whole-alloca integer loads and stores unsplittable just as they have historically been, repartition and rewrite. The result is that when there are integer loads and stores anywhere within an alloca (such as from a memcpy of a sub-object of a larger object), we can split them up if there are non-integer components to the aggregate hiding beneath. I've added the challenging test cases to demonstrate how this is able to promote to scalars even a case where we have even *partially* overlapping loads and stores. This restores the single-store behavior for small arrays of i8s which is really nice. I've restored both the little endian testing and big endian testing for these exactly as they were prior to r225061. It also forced me to be more aggressive in an alignment test to actually defeat SROA. =] Without the added volatiles there, we actually split up the weird i16 loads and produce nice double allocas with better alignment. This also uncovered a number of bugs where we failed to handle splittable load and store slices which didn't have a begininng offset of zero. Those fixes are included, and without them the existing test cases explode in glorious fireworks. =] I've kept support for leaving whole-alloca integer loads and stores as splittable even for the purpose of rewriting, but I think that's likely no longer needed. With the new pre-splitting, we might be able to remove all the splitting support for loads and stores from the rewriter. Not doing that in this patch to try to isolate any performance regressions that causes in an easy to find and revert chunk. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225074 91177308-0d34-0410-b5e6-96231b3b80d8
115 lines
3.8 KiB
LLVM
115 lines
3.8 KiB
LLVM
; RUN: opt < %s -sroa -S | FileCheck %s
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; RUN: opt < %s -sroa -force-ssa-updater -S | FileCheck %s
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target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n8:16:32:64"
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define i8 @test1() {
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; We fully promote these to the i24 load or store size, resulting in just masks
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; and other operations that instcombine will fold, but no alloca. Note this is
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; the same as test12 in basictest.ll, but here we assert big-endian byte
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; ordering.
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;
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; CHECK-LABEL: @test1(
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entry:
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%a = alloca [3 x i8]
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%b = alloca [3 x i8]
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; CHECK-NOT: alloca
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%a0ptr = getelementptr [3 x i8]* %a, i64 0, i32 0
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store i8 0, i8* %a0ptr
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%a1ptr = getelementptr [3 x i8]* %a, i64 0, i32 1
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store i8 0, i8* %a1ptr
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%a2ptr = getelementptr [3 x i8]* %a, i64 0, i32 2
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store i8 0, i8* %a2ptr
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%aiptr = bitcast [3 x i8]* %a to i24*
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%ai = load i24* %aiptr
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; CHECK-NOT: store
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; CHECK-NOT: load
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; CHECK: %[[ext2:.*]] = zext i8 0 to i24
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; CHECK-NEXT: %[[mask2:.*]] = and i24 undef, -256
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; CHECK-NEXT: %[[insert2:.*]] = or i24 %[[mask2]], %[[ext2]]
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; CHECK-NEXT: %[[ext1:.*]] = zext i8 0 to i24
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; CHECK-NEXT: %[[shift1:.*]] = shl i24 %[[ext1]], 8
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; CHECK-NEXT: %[[mask1:.*]] = and i24 %[[insert2]], -65281
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; CHECK-NEXT: %[[insert1:.*]] = or i24 %[[mask1]], %[[shift1]]
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; CHECK-NEXT: %[[ext0:.*]] = zext i8 0 to i24
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; CHECK-NEXT: %[[shift0:.*]] = shl i24 %[[ext0]], 16
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; CHECK-NEXT: %[[mask0:.*]] = and i24 %[[insert1]], 65535
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; CHECK-NEXT: %[[insert0:.*]] = or i24 %[[mask0]], %[[shift0]]
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%biptr = bitcast [3 x i8]* %b to i24*
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store i24 %ai, i24* %biptr
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%b0ptr = getelementptr [3 x i8]* %b, i64 0, i32 0
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%b0 = load i8* %b0ptr
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%b1ptr = getelementptr [3 x i8]* %b, i64 0, i32 1
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%b1 = load i8* %b1ptr
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%b2ptr = getelementptr [3 x i8]* %b, i64 0, i32 2
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%b2 = load i8* %b2ptr
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; CHECK-NOT: store
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; CHECK-NOT: load
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; CHECK: %[[shift0:.*]] = lshr i24 %[[insert0]], 16
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; CHECK-NEXT: %[[trunc0:.*]] = trunc i24 %[[shift0]] to i8
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; CHECK-NEXT: %[[shift1:.*]] = lshr i24 %[[insert0]], 8
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; CHECK-NEXT: %[[trunc1:.*]] = trunc i24 %[[shift1]] to i8
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; CHECK-NEXT: %[[trunc2:.*]] = trunc i24 %[[insert0]] to i8
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%bsum0 = add i8 %b0, %b1
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%bsum1 = add i8 %bsum0, %b2
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ret i8 %bsum1
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; CHECK: %[[sum0:.*]] = add i8 %[[trunc0]], %[[trunc1]]
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; CHECK-NEXT: %[[sum1:.*]] = add i8 %[[sum0]], %[[trunc2]]
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; CHECK-NEXT: ret i8 %[[sum1]]
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}
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define i64 @test2() {
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; Test for various mixed sizes of integer loads and stores all getting
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; promoted.
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;
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; CHECK-LABEL: @test2(
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entry:
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%a = alloca [7 x i8]
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; CHECK-NOT: alloca
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%a0ptr = getelementptr [7 x i8]* %a, i64 0, i32 0
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%a1ptr = getelementptr [7 x i8]* %a, i64 0, i32 1
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%a2ptr = getelementptr [7 x i8]* %a, i64 0, i32 2
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%a3ptr = getelementptr [7 x i8]* %a, i64 0, i32 3
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; CHECK-NOT: store
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; CHECK-NOT: load
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%a0i16ptr = bitcast i8* %a0ptr to i16*
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store i16 1, i16* %a0i16ptr
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store i8 1, i8* %a2ptr
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; CHECK: %[[mask1:.*]] = and i40 undef, 4294967295
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; CHECK-NEXT: %[[insert1:.*]] = or i40 %[[mask1]], 4294967296
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%a3i24ptr = bitcast i8* %a3ptr to i24*
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store i24 1, i24* %a3i24ptr
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; CHECK-NEXT: %[[mask2:.*]] = and i40 %[[insert1]], -4294967041
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; CHECK-NEXT: %[[insert2:.*]] = or i40 %[[mask2]], 256
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%a2i40ptr = bitcast i8* %a2ptr to i40*
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store i40 1, i40* %a2i40ptr
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; CHECK-NEXT: %[[ext3:.*]] = zext i40 1 to i56
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; CHECK-NEXT: %[[mask3:.*]] = and i56 undef, -1099511627776
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; CHECK-NEXT: %[[insert3:.*]] = or i56 %[[mask3]], %[[ext3]]
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; CHECK-NOT: store
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; CHECK-NOT: load
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%aiptr = bitcast [7 x i8]* %a to i56*
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%ai = load i56* %aiptr
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%ret = zext i56 %ai to i64
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ret i64 %ret
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; CHECK-NEXT: %[[ext4:.*]] = zext i16 1 to i56
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; CHECK-NEXT: %[[shift4:.*]] = shl i56 %[[ext4]], 40
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; CHECK-NEXT: %[[mask4:.*]] = and i56 %[[insert3]], 1099511627775
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; CHECK-NEXT: %[[insert4:.*]] = or i56 %[[mask4]], %[[shift4]]
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; CHECK-NEXT: %[[ret:.*]] = zext i56 %[[insert4]] to i64
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; CHECK-NEXT: ret i64 %[[ret]]
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}
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