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e4709777e3
These copies would coalesce easily, but the resulting value would be defined by a deleted instruction. Now we also remove the undefined value number from the destination register. This fixes PR10503. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136174 91177308-0d34-0410-b5e6-96231b3b80d8
247 lines
10 KiB
C++
247 lines
10 KiB
C++
//===-- RegisterCoalescer.h - Register Coalescing Interface ------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the abstract interface for register coalescers,
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// allowing them to interact with and query register allocators.
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//
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//===----------------------------------------------------------------------===//
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#include "RegisterClassInfo.h"
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#include "llvm/Support/IncludeFile.h"
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#include "llvm/CodeGen/LiveInterval.h"
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#include "llvm/ADT/SmallPtrSet.h"
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#ifndef LLVM_CODEGEN_REGISTER_COALESCER_H
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#define LLVM_CODEGEN_REGISTER_COALESCER_H
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namespace llvm {
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class MachineFunction;
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class RegallocQuery;
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class AnalysisUsage;
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class MachineInstr;
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class TargetRegisterInfo;
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class TargetRegisterClass;
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class TargetInstrInfo;
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class LiveDebugVariables;
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class VirtRegMap;
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class MachineLoopInfo;
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class CoalescerPair;
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/// An abstract interface for register coalescers. Coalescers must
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/// implement this interface to be part of the coalescer analysis
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/// group.
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class RegisterCoalescer : public MachineFunctionPass {
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MachineFunction* mf_;
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MachineRegisterInfo* mri_;
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const TargetMachine* tm_;
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const TargetRegisterInfo* tri_;
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const TargetInstrInfo* tii_;
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LiveIntervals *li_;
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LiveDebugVariables *ldv_;
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const MachineLoopInfo* loopInfo;
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AliasAnalysis *AA;
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RegisterClassInfo RegClassInfo;
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/// JoinedCopies - Keep track of copies eliminated due to coalescing.
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///
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SmallPtrSet<MachineInstr*, 32> JoinedCopies;
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/// ReMatCopies - Keep track of copies eliminated due to remat.
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///
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SmallPtrSet<MachineInstr*, 32> ReMatCopies;
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/// ReMatDefs - Keep track of definition instructions which have
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/// been remat'ed.
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SmallPtrSet<MachineInstr*, 8> ReMatDefs;
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/// joinIntervals - join compatible live intervals
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void joinIntervals();
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/// CopyCoalesceInMBB - Coalesce copies in the specified MBB, putting
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/// copies that cannot yet be coalesced into the "TryAgain" list.
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void CopyCoalesceInMBB(MachineBasicBlock *MBB,
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std::vector<MachineInstr*> &TryAgain);
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/// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
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/// which are the src/dst of the copy instruction CopyMI. This returns true
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/// if the copy was successfully coalesced away. If it is not currently
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/// possible to coalesce this interval, but it may be possible if other
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/// things get coalesced, then it returns true by reference in 'Again'.
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bool JoinCopy(MachineInstr *TheCopy, bool &Again);
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/// JoinIntervals - Attempt to join these two intervals. On failure, this
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/// returns false. The output "SrcInt" will not have been modified, so we can
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/// use this information below to update aliases.
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bool JoinIntervals(CoalescerPair &CP);
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/// AdjustCopiesBackFrom - We found a non-trivially-coalescable copy. If
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/// the source value number is defined by a copy from the destination reg
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/// see if we can merge these two destination reg valno# into a single
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/// value number, eliminating a copy.
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bool AdjustCopiesBackFrom(const CoalescerPair &CP, MachineInstr *CopyMI);
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/// HasOtherReachingDefs - Return true if there are definitions of IntB
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/// other than BValNo val# that can reach uses of AValno val# of IntA.
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bool HasOtherReachingDefs(LiveInterval &IntA, LiveInterval &IntB,
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VNInfo *AValNo, VNInfo *BValNo);
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/// RemoveCopyByCommutingDef - We found a non-trivially-coalescable copy.
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/// If the source value number is defined by a commutable instruction and
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/// its other operand is coalesced to the copy dest register, see if we
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/// can transform the copy into a noop by commuting the definition.
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bool RemoveCopyByCommutingDef(const CoalescerPair &CP,MachineInstr *CopyMI);
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/// ReMaterializeTrivialDef - If the source of a copy is defined by a trivial
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/// computation, replace the copy by rematerialize the definition.
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/// If PreserveSrcInt is true, make sure SrcInt is valid after the call.
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bool ReMaterializeTrivialDef(LiveInterval &SrcInt, bool PreserveSrcInt,
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unsigned DstReg, unsigned DstSubIdx,
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MachineInstr *CopyMI);
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/// shouldJoinPhys - Return true if a physreg copy should be joined.
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bool shouldJoinPhys(CoalescerPair &CP);
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/// isWinToJoinCrossClass - Return true if it's profitable to coalesce
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/// two virtual registers from different register classes.
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bool isWinToJoinCrossClass(unsigned SrcReg,
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unsigned DstReg,
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const TargetRegisterClass *SrcRC,
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const TargetRegisterClass *DstRC,
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const TargetRegisterClass *NewRC);
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/// UpdateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and
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/// update the subregister number if it is not zero. If DstReg is a
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/// physical register and the existing subregister number of the def / use
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/// being updated is not zero, make sure to set it to the correct physical
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/// subregister.
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void UpdateRegDefsUses(const CoalescerPair &CP);
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/// RemoveDeadDef - If a def of a live interval is now determined dead,
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/// remove the val# it defines. If the live interval becomes empty, remove
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/// it as well.
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bool RemoveDeadDef(LiveInterval &li, MachineInstr *DefMI);
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/// RemoveCopyFlag - If DstReg is no longer defined by CopyMI, clear the
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/// VNInfo copy flag for DstReg and all aliases.
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void RemoveCopyFlag(unsigned DstReg, const MachineInstr *CopyMI);
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/// markAsJoined - Remember that CopyMI has already been joined.
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void markAsJoined(MachineInstr *CopyMI);
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/// eliminateUndefCopy - Handle copies of undef values.
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bool eliminateUndefCopy(MachineInstr *CopyMI, const CoalescerPair &CP);
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public:
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static char ID; // Class identification, replacement for typeinfo
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RegisterCoalescer() : MachineFunctionPass(ID) {
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initializeRegisterCoalescerPass(*PassRegistry::getPassRegistry());
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}
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/// Register allocators must call this from their own
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/// getAnalysisUsage to cover the case where the coalescer is not
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/// a Pass in the proper sense and isn't managed by PassManager.
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/// PassManager needs to know which analyses to make available and
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/// which to invalidate when running the register allocator or any
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/// pass that might call coalescing. The long-term solution is to
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/// allow hierarchies of PassManagers.
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virtual void getAnalysisUsage(AnalysisUsage &AU) const;
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virtual void releaseMemory();
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/// runOnMachineFunction - pass entry point
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virtual bool runOnMachineFunction(MachineFunction&);
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/// print - Implement the dump method.
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virtual void print(raw_ostream &O, const Module* = 0) const;
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};
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/// CoalescerPair - A helper class for register coalescers. When deciding if
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/// two registers can be coalesced, CoalescerPair can determine if a copy
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/// instruction would become an identity copy after coalescing.
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class CoalescerPair {
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const TargetInstrInfo &tii_;
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const TargetRegisterInfo &tri_;
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/// dstReg_ - The register that will be left after coalescing. It can be a
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/// virtual or physical register.
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unsigned dstReg_;
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/// srcReg_ - the virtual register that will be coalesced into dstReg.
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unsigned srcReg_;
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/// subReg_ - The subregister index of srcReg in dstReg_. It is possible the
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/// coalesce srcReg_ into a subreg of the larger dstReg_ when dstReg_ is a
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/// virtual register.
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unsigned subIdx_;
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/// partial_ - True when the original copy was a partial subregister copy.
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bool partial_;
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/// crossClass_ - True when both regs are virtual, and newRC is constrained.
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bool crossClass_;
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/// flipped_ - True when DstReg and SrcReg are reversed from the oriignal copy
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/// instruction.
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bool flipped_;
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/// newRC_ - The register class of the coalesced register, or NULL if dstReg_
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/// is a physreg.
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const TargetRegisterClass *newRC_;
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public:
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CoalescerPair(const TargetInstrInfo &tii, const TargetRegisterInfo &tri)
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: tii_(tii), tri_(tri), dstReg_(0), srcReg_(0), subIdx_(0),
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partial_(false), crossClass_(false), flipped_(false), newRC_(0) {}
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/// setRegisters - set registers to match the copy instruction MI. Return
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/// false if MI is not a coalescable copy instruction.
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bool setRegisters(const MachineInstr*);
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/// flip - Swap srcReg_ and dstReg_. Return false if swapping is impossible
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/// because dstReg_ is a physical register, or subIdx_ is set.
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bool flip();
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/// isCoalescable - Return true if MI is a copy instruction that will become
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/// an identity copy after coalescing.
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bool isCoalescable(const MachineInstr*) const;
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/// isPhys - Return true if DstReg is a physical register.
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bool isPhys() const { return !newRC_; }
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/// isPartial - Return true if the original copy instruction did not copy the
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/// full register, but was a subreg operation.
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bool isPartial() const { return partial_; }
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/// isCrossClass - Return true if DstReg is virtual and NewRC is a smaller register class than DstReg's.
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bool isCrossClass() const { return crossClass_; }
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/// isFlipped - Return true when getSrcReg is the register being defined by
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/// the original copy instruction.
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bool isFlipped() const { return flipped_; }
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/// getDstReg - Return the register (virtual or physical) that will remain
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/// after coalescing.
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unsigned getDstReg() const { return dstReg_; }
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/// getSrcReg - Return the virtual register that will be coalesced away.
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unsigned getSrcReg() const { return srcReg_; }
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/// getSubIdx - Return the subregister index in DstReg that SrcReg will be
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/// coalesced into, or 0.
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unsigned getSubIdx() const { return subIdx_; }
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/// getNewRC - Return the register class of the coalesced register.
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const TargetRegisterClass *getNewRC() const { return newRC_; }
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};
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} // End llvm namespace
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#endif
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