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that it is cheap and efficient to get. Move a variety of predicates from TargetInstrInfo into TargetInstrDescriptor, which makes it much easier to query a predicate when you don't have TII around. Now you can use MI->getDesc()->isBranch() instead of going through TII, and this is much more efficient anyway. Not all of the predicates have been moved over yet. Update old code that used MI->getInstrDescriptor()->Flags to use the new predicates in many places. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45674 91177308-0d34-0410-b5e6-96231b3b80d8
208 lines
7.6 KiB
C++
208 lines
7.6 KiB
C++
//===-- llvm/CodeGen/MachineInstr.h - MachineInstr class --------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the declaration of the MachineInstr class, which is the
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// basic representation for all target dependent machine instructions used by
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// the back end.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_MACHINEINSTR_H
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#define LLVM_CODEGEN_MACHINEINSTR_H
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#include "llvm/CodeGen/MachineOperand.h"
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namespace llvm {
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class TargetInstrDescriptor;
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template <typename T> struct ilist_traits;
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template <typename T> struct ilist;
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//===----------------------------------------------------------------------===//
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/// MachineInstr - Representation of each machine instruction.
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///
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class MachineInstr {
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const TargetInstrDescriptor *TID; // Instruction descriptor.
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unsigned short NumImplicitOps; // Number of implicit operands (which
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// are determined at construction time).
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std::vector<MachineOperand> Operands; // the operands
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MachineInstr *Prev, *Next; // Links for MBB's intrusive list.
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MachineBasicBlock *Parent; // Pointer to the owning basic block.
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// OperandComplete - Return true if it's illegal to add a new operand
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bool OperandsComplete() const;
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MachineInstr(const MachineInstr&);
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void operator=(const MachineInstr&); // DO NOT IMPLEMENT
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// Intrusive list support
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friend struct ilist_traits<MachineInstr>;
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friend struct ilist_traits<MachineBasicBlock>;
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void setParent(MachineBasicBlock *P) { Parent = P; }
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public:
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/// MachineInstr ctor - This constructor creates a dummy MachineInstr with
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/// TID NULL and no operands.
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MachineInstr();
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/// MachineInstr ctor - This constructor create a MachineInstr and add the
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/// implicit operands. It reserves space for number of operands specified by
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/// TargetInstrDescriptor.
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explicit MachineInstr(const TargetInstrDescriptor &TID, bool NoImp = false);
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/// MachineInstr ctor - Work exactly the same as the ctor above, except that
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/// the MachineInstr is created and added to the end of the specified basic
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/// block.
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///
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MachineInstr(MachineBasicBlock *MBB, const TargetInstrDescriptor &TID);
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~MachineInstr();
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const MachineBasicBlock* getParent() const { return Parent; }
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MachineBasicBlock* getParent() { return Parent; }
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/// getDesc - Returns the target instruction descriptor of this
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/// MachineInstr.
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const TargetInstrDescriptor *getDesc() const { return TID; }
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/// getOpcode - Returns the opcode of this MachineInstr.
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///
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int getOpcode() const;
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/// Access to explicit operands of the instruction.
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///
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unsigned getNumOperands() const { return Operands.size(); }
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const MachineOperand& getOperand(unsigned i) const {
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assert(i < getNumOperands() && "getOperand() out of range!");
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return Operands[i];
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}
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MachineOperand& getOperand(unsigned i) {
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assert(i < getNumOperands() && "getOperand() out of range!");
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return Operands[i];
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}
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/// getNumExplicitOperands - Returns the number of non-implicit operands.
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///
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unsigned getNumExplicitOperands() const;
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/// isIdenticalTo - Return true if this instruction is identical to (same
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/// opcode and same operands as) the specified instruction.
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bool isIdenticalTo(const MachineInstr *Other) const {
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if (Other->getOpcode() != getOpcode() ||
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Other->getNumOperands() != getNumOperands())
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return false;
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for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
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if (!getOperand(i).isIdenticalTo(Other->getOperand(i)))
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return false;
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return true;
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}
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/// clone - Create a copy of 'this' instruction that is identical in
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/// all ways except the the instruction has no parent, prev, or next.
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MachineInstr* clone() const { return new MachineInstr(*this); }
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/// removeFromParent - This method unlinks 'this' from the containing basic
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/// block, and returns it, but does not delete it.
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MachineInstr *removeFromParent();
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/// eraseFromParent - This method unlinks 'this' from the containing basic
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/// block and deletes it.
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void eraseFromParent() {
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delete removeFromParent();
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}
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/// findRegisterUseOperandIdx() - Returns the operand index that is a use of
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/// the specific register or -1 if it is not found. It further tightening
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/// the search criteria to a use that kills the register if isKill is true.
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int findRegisterUseOperandIdx(unsigned Reg, bool isKill = false) const;
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/// findRegisterDefOperand() - Returns the MachineOperand that is a def of
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/// the specific register or NULL if it is not found.
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MachineOperand *findRegisterDefOperand(unsigned Reg);
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/// findFirstPredOperandIdx() - Find the index of the first operand in the
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/// operand list that is used to represent the predicate. It returns -1 if
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/// none is found.
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int findFirstPredOperandIdx() const;
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/// isRegReDefinedByTwoAddr - Returns true if the Reg re-definition is due
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/// to two addr elimination.
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bool isRegReDefinedByTwoAddr(unsigned Reg) const;
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/// copyKillDeadInfo - Copies kill / dead operand properties from MI.
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///
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void copyKillDeadInfo(const MachineInstr *MI);
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/// copyPredicates - Copies predicate operand(s) from MI.
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void copyPredicates(const MachineInstr *MI);
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//
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// Debugging support
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//
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void print(std::ostream *OS, const TargetMachine *TM) const {
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if (OS) print(*OS, TM);
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}
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void print(std::ostream &OS, const TargetMachine *TM = 0) const;
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void print(std::ostream *OS) const { if (OS) print(*OS); }
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void dump() const;
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//===--------------------------------------------------------------------===//
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// Accessors used to build up machine instructions.
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/// addOperand - Add the specified operand to the instruction. If it is an
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/// implicit operand, it is added to the end of the operand list. If it is
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/// an explicit operand it is added at the end of the explicit operand list
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/// (before the first implicit operand).
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void addOperand(const MachineOperand &Op);
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/// setInstrDescriptor - Replace the instruction descriptor (thus opcode) of
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/// the current instruction with a new one.
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///
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void setInstrDescriptor(const TargetInstrDescriptor &tid) { TID = &tid; }
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/// RemoveOperand - Erase an operand from an instruction, leaving it with one
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/// fewer operand than it started with.
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///
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void RemoveOperand(unsigned i);
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private:
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/// getRegInfo - If this instruction is embedded into a MachineFunction,
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/// return the MachineRegisterInfo object for the current function, otherwise
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/// return null.
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MachineRegisterInfo *getRegInfo();
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/// addImplicitDefUseOperands - Add all implicit def and use operands to
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/// this instruction.
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void addImplicitDefUseOperands();
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/// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
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/// this instruction from their respective use lists. This requires that the
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/// operands already be on their use lists.
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void RemoveRegOperandsFromUseLists();
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/// AddRegOperandsToUseLists - Add all of the register operands in
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/// this instruction from their respective use lists. This requires that the
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/// operands not be on their use lists yet.
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void AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo);
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};
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//===----------------------------------------------------------------------===//
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// Debugging Support
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inline std::ostream& operator<<(std::ostream &OS, const MachineInstr &MI) {
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MI.print(OS);
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return OS;
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}
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} // End llvm namespace
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#endif
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