Manman Ren 692d1830f3 Register Allocator: check other options before using a CSR for the first time. ... When register allocator's stage is RS_Spill, we choose spill over using the CSR for the first time, if the spill cost is lower than CSRCost. When register allocator's stage is < RS_Split, we choose pre-splitting over using the CSR for the first time, if the cost of splitting is lower than CSRCost. CSRCost is set with command-line option "regalloc-csr-first-time-cost". The default value is 0 to generate the same codes as before this commit. With a value of 15 (1 << 14 is the entry frequency), I measured performance gain of 3% on 253.perlbmk and 1.7% on 197.parser, with instrumented PGO, on an arm device. rdar://16162005 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204690 91177308-0d34-0410-b5e6-96231b3b80d8		2014-03-25 00:16:25 +00:00
..
AArch64	Register Allocator: check other options before using a CSR for the first time.	2014-03-25 00:16:25 +00:00
ARM	Fix test command line to avoid generating output file.	2014-03-21 07:20:29 +00:00
CPP
Generic
Hexagon
Inputs
Mips	[mips] Correct lowering of VECTOR_SHUFFLE to VSHF.	2014-03-21 16:56:51 +00:00
MSP430
NVPTX	Add test to test/CodeGen/NVPTX for "alloca buffer" arguments.	2014-03-24 16:52:30 +00:00
PowerPC	[PowerPC] Make use of VSX f64 <-> i64 conversion instructions	2014-03-23 05:35:00 +00:00
R600	R600/SI: Fix extra mov from legalizing 64-bit SALU ops.	2014-03-24 20:08:13 +00:00
SPARC
SystemZ	[SystemZ] Add support for z196 float<->unsigned conversions	2014-03-21 10:56:30 +00:00
Thumb
Thumb2
X86	[X86][ISelDAG] Add missing fallback patterns for avx2 broadcast instructions.	2014-03-24 17:54:19 +00:00
XCore