Tom Stellard 692ee102eb R600: Add 64-bit float load/store support ... * Added R600_Reg64 class * Added T#Index#.XY registers definition * Added v2i32 register reads from parameter and global space * Added f32 and i32 elements extraction from v2f32 and v2i32 * Added v2i32 -> v2f32 conversions Tom Stellard: - Mark vec2 operations as expand. The addition of a vec2 register class made them all legal. Patch by: Dmitry Cherkassov Signed-off-by: Dmitry Cherkassov <dcherkassov@gmail.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187582 91177308-0d34-0410-b5e6-96231b3b80d8		2013-08-01 15:23:42 +00:00
..
Analysis	Fix a severe compile time problem when forming large SCEV expressions.	2013-07-31 02:43:40 +00:00
AsmParser
Bitcode
CodeGen	Fix crashing on invalid inline asm with matching constraints.	2013-07-31 01:26:24 +00:00
DebugInfo
ExecutionEngine
IR	Reject bitcasts between address spaces with different sizes	2013-07-31 17:49:08 +00:00
IRReader
Linker
MC
Object	Add support for the 's' operation to llvm-ar.	2013-07-29 12:40:31 +00:00
Option	Option parsing: add support for alias arguments.	2013-07-31 22:44:41 +00:00
Support	Fix windows' implementation of status when a file doesn't exist.	2013-07-31 00:10:25 +00:00
TableGen
Target	R600: Add 64-bit float load/store support	2013-08-01 15:23:42 +00:00
Transforms	80-col	2013-07-31 22:17:45 +00:00
CMakeLists.txt
LLVMBuild.txt
Makefile