Andrew Trick b6b5b7b691 LSR: fix expansion of scaled reg in non-address type formulae. ...

For non-address users, Base and Scaled registers are not specially
associated to fit an address mode, so SCEVExpander should apply normal
expansion rules. Otherwise we may sink computation into inner loops
that have already been optimized.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158537 91177308-0d34-0410-b5e6-96231b3b80d8

2012-06-15 20:07:29 +00:00

..

Hello

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InstCombine

InstCombine: fix a bug when combining (fcmp cc0 x, y) && (fcmp cc1 x, y).

2012-06-14 05:57:42 +00:00

Instrumentation

Register the gcov "writeout" at init time. Don't list this as a d'tor. Instead,

2012-06-01 23:14:32 +00:00

IPO

Some optimizations done by globalopt are safe only for internal linkage, not

2012-06-15 18:00:24 +00:00

Scalar

LSR: fix expansion of scaled reg in non-address type formulae.

2012-06-15 20:07:29 +00:00

Utils

SimplifyCFG: fold unconditional branch to its predecessor if profitable.

2012-06-13 05:43:29 +00:00

Vectorize

Don't vectorize target-specific types (ppc_fp128, x86_fp80, etc.).

2012-04-27 19:34:00 +00:00

CMakeLists.txt

Add a basic-block autovectorization pass.

2012-02-01 03:51:43 +00:00

LLVMBuild.txt

Add a basic-block autovectorization pass.

2012-02-01 03:51:43 +00:00

Makefile

Add a basic-block autovectorization pass.

2012-02-01 03:51:43 +00:00