Matt Arsenault 69643f47ad R600/SI: Add failing testcase reduced from OpenCV ... This fails the verifier with: "Expected a VCSrc_32 register, but got a VReg_1 register" git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220368 91177308-0d34-0410-b5e6-96231b3b80d8		2014-10-22 04:26:10 +00:00
..
AArch64	[PBQP] Teach PassConfig to tell if the default register allocator is used.	2014-10-21 20:47:22 +00:00
ARM	ARM: rework Thumb1 frame index rewriting	2014-10-20 21:28:41 +00:00
CPP
Generic
Hexagon
Inputs
Mips
MSP430
NVPTX
PowerPC	Add minnum / maxnum codegen	2014-10-21 23:01:01 +00:00
R600	R600/SI: Add failing testcase reduced from OpenCV	2014-10-22 04:26:10 +00:00
SPARC
SystemZ
Thumb	[Thumb] Fix crash in Thumb1RegisterInfo::rewriteFrameIndex	2014-10-20 11:00:18 +00:00
Thumb2	ARM: Fix a bug which was causing convergence failure in constant-island pass.	2014-10-17 01:31:47 +00:00
X86	Add minnum / maxnum codegen	2014-10-21 23:01:01 +00:00
XCore	Fix a bit of confusion about .set and produce more readable assembly.	2014-10-21 01:17:30 +00:00