llvm-6502/test/CodeGen/ARM/2010-12-15-elf-lcomm.ll
Ahmed Bougacha c9ad3ab624 [AArch64, ARM] Enable GlobalMerge with -O3 rather than -O1.
The pass used to be enabled by default with CodeGenOpt::Less (-O1).
This is too aggressive, considering the pass indiscriminately merges
all globals together.

Currently, performance doesn't always improve, and, on code that uses
few globals (e.g., the odd file- or function- static), more often than
not is degraded by the optimization.  Lengthy discussion can be found
on llvmdev (AArch64-focused;  ARM has similar problems):
  http://lists.cs.uiuc.edu/pipermail/llvmdev/2015-February/082800.html
Also, it makes tooling and debuggers less useful when dealing with
globals and data sections.

GlobalMerge needs to better identify those cases that benefit, and this
will be done separately.  In the meantime, move the pass to run with
-O3 rather than -O1, on both ARM and AArch64.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233024 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-23 21:17:36 +00:00

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LLVM

; RUN: llc %s -mtriple=armv7-linux-gnueabi -O3 -filetype=obj -o - | \
; RUN: llvm-readobj -s -t | FileCheck -check-prefix=OBJ %s
; RUN: llc %s -mtriple=armv7-linux-gnueabi -O3 -o - | \
; RUN: FileCheck -check-prefix=ASM %s
@dummy = internal global i32 666
@array00 = internal global [80 x i8] zeroinitializer, align 1
@sum = internal global i32 55
@STRIDE = internal global i32 8
; ASM: .type array00,%object @ @array00
; ASM-NEXT: .local array00
; ASM-NEXT: .comm array00,80,1
; ASM-NEXT: .type _MergedGlobals,%object @ @_MergedGlobals
; OBJ: Sections [
; OBJ: Section {
; OBJ: Index: 4
; OBJ-NEXT: Name: .bss
; OBJ: Symbols [
; OBJ: Symbol {
; OBJ: Name: array00
; OBJ-NEXT: Value: 0x0
; OBJ-NEXT: Size: 80
; OBJ-NEXT: Binding: Local
; OBJ-NEXT: Type: Object
; OBJ-NEXT: Other: 0
; OBJ-NEXT: Section: .bss
define i32 @main(i32 %argc) nounwind {
%1 = load i32, i32* @sum, align 4
%2 = getelementptr [80 x i8], [80 x i8]* @array00, i32 0, i32 %argc
%3 = load i8, i8* %2
%4 = zext i8 %3 to i32
%5 = add i32 %1, %4
ret i32 %5
}