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https://github.com/c64scene-ar/llvm-6502.git
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40e455d992
SI_IF and SI_ELSE are terminators which also produce a value. For these instructions ISel always inserts a COPY to move their value to another basic block. This COPY ends up between SI_(IF|ELSE) and the S_BRANCH* instruction at the end of the block. This breaks MachineBasicBlock::getFirstTerminator() and also the machine verifier which assumes that terminators are grouped together at the end of blocks. To solve this we coalesce the copy away right after ISel to make sure there are no instructions in between terminators at the end of blocks. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207591 91177308-0d34-0410-b5e6-96231b3b80d8
85 lines
2.8 KiB
LLVM
85 lines
2.8 KiB
LLVM
; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI %s
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declare i32 @llvm.r600.read.tidig.x() readnone
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; SI-LABEL: @test_i64_vreg:
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; SI: V_ADD_I32
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; SI: V_ADDC_U32
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define void @test_i64_vreg(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %inA, i64 addrspace(1)* noalias %inB) {
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%tid = call i32 @llvm.r600.read.tidig.x() readnone
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%a_ptr = getelementptr i64 addrspace(1)* %inA, i32 %tid
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%b_ptr = getelementptr i64 addrspace(1)* %inB, i32 %tid
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%a = load i64 addrspace(1)* %a_ptr
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%b = load i64 addrspace(1)* %b_ptr
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%result = add i64 %a, %b
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store i64 %result, i64 addrspace(1)* %out
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ret void
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}
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; Check that the SGPR add operand is correctly moved to a VGPR.
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; SI-LABEL: @sgpr_operand:
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; SI: V_ADD_I32
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; SI: V_ADDC_U32
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define void @sgpr_operand(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in, i64 addrspace(1)* noalias %in_bar, i64 %a) {
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%foo = load i64 addrspace(1)* %in, align 8
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%result = add i64 %foo, %a
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store i64 %result, i64 addrspace(1)* %out
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ret void
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}
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; Swap the arguments. Check that the SGPR -> VGPR copy works with the
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; SGPR as other operand.
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;
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; SI-LABEL: @sgpr_operand_reversed:
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; SI: V_ADD_I32
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; SI: V_ADDC_U32
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define void @sgpr_operand_reversed(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in, i64 %a) {
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%foo = load i64 addrspace(1)* %in, align 8
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%result = add i64 %a, %foo
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store i64 %result, i64 addrspace(1)* %out
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ret void
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}
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; SI-LABEL: @test_v2i64_sreg:
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; SI: S_ADD_I32
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; SI: S_ADDC_U32
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; SI: S_ADD_I32
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; SI: S_ADDC_U32
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define void @test_v2i64_sreg(<2 x i64> addrspace(1)* noalias %out, <2 x i64> %a, <2 x i64> %b) {
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%result = add <2 x i64> %a, %b
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store <2 x i64> %result, <2 x i64> addrspace(1)* %out
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ret void
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}
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; SI-LABEL: @test_v2i64_vreg:
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; SI: V_ADD_I32
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; SI: V_ADDC_U32
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; SI: V_ADD_I32
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; SI: V_ADDC_U32
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define void @test_v2i64_vreg(<2 x i64> addrspace(1)* noalias %out, <2 x i64> addrspace(1)* noalias %inA, <2 x i64> addrspace(1)* noalias %inB) {
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%tid = call i32 @llvm.r600.read.tidig.x() readnone
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%a_ptr = getelementptr <2 x i64> addrspace(1)* %inA, i32 %tid
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%b_ptr = getelementptr <2 x i64> addrspace(1)* %inB, i32 %tid
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%a = load <2 x i64> addrspace(1)* %a_ptr
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%b = load <2 x i64> addrspace(1)* %b_ptr
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%result = add <2 x i64> %a, %b
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store <2 x i64> %result, <2 x i64> addrspace(1)* %out
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ret void
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}
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; SI-LABEL: @trunc_i64_add_to_i32
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; SI: S_LOAD_DWORD [[SREG0:s[0-9]+]],
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; SI: S_LOAD_DWORD [[SREG1:s[0-9]+]],
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; SI: S_ADD_I32 [[SRESULT:s[0-9]+]], [[SREG1]], [[SREG0]]
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; SI-NOT: ADDC
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; SI: V_MOV_B32_e32 [[VRESULT:v[0-9]+]], [[SRESULT]]
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; SI: BUFFER_STORE_DWORD [[VRESULT]],
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define void @trunc_i64_add_to_i32(i32 addrspace(1)* %out, i64 %a, i64 %b) {
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%add = add i64 %b, %a
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%trunc = trunc i64 %add to i32
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store i32 %trunc, i32 addrspace(1)* %out, align 8
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ret void
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}
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