Aaron Watry 69d3a40298 R600: Add v2i32 test for vselect ... Note: Only adding test for evergreen, not SI yet. When I attempted to expand vselect for SI, I got the following: llc: /home/awatry/src/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp:522: llvm::SDValue llvm::DAGTypeLegalizer::PromoteIntRes_SETCC(llvm::SDNode*): Assertion `SVT.isVector() == N->getOperand(0).getValueType().isVector() && "Vector compare must return a vector result!"' failed. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184847 91177308-0d34-0410-b5e6-96231b3b80d8		2013-06-25 13:55:54 +00:00
..
AArch64	AArch64: remove accidental test output file.	2013-06-18 21:16:53 +00:00
ARM	DebugInfo: Don't lose unreferenced non-trivial by-value parameters	2013-06-21 22:56:30 +00:00
CPP
Generic	Drop @llvm.annotation and @llvm.ptr.annotation intrinsics during codegen.	2013-05-21 14:37:16 +00:00
Hexagon	Hexagon: Pass to replace tranfer/copy instructions into combine instruction	2013-05-14 18:54:06 +00:00
Inputs
MBlaze
Mips	Replace with a shorter test case produced by Doug Gillmore.	2013-06-22 19:35:08 +00:00
MSP430	DAGCombiner: Simplify inverted bit tests	2013-05-08 06:44:42 +00:00
NVPTX	[NVPTX] Add support for selecting CUDA vs OCL mode based on triple	2013-06-21 18:51:49 +00:00
PowerPC	[PowerPC] Disable fast-isel for existing -O0 tests for PowerPC.	2013-06-13 20:23:34 +00:00
R600	R600: Add v2i32 test for vselect	2013-06-25 13:55:54 +00:00
SI
SPARC	Switch spill weights from a basic loop depth estimation to BlockFrequencyInfo.	2013-06-17 19:00:36 +00:00
SystemZ	[SystemZ] Don't use LOAD and STORE REVERSED for volatile accesses	2013-05-31 13:25:22 +00:00
Thumb	LocalStackSlotAllocation improvements	2013-04-30 20:04:37 +00:00
Thumb2	Cortex-R5 can issue Thumb2 integer division instructions.	2013-06-04 22:52:09 +00:00
X86	Revert "Temporarily enable MI-Sched on X86."	2013-06-25 02:48:58 +00:00
XCore	[XCore] Fix handling of functions where only the LR is spilled.	2013-05-09 16:43:42 +00:00