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https://github.com/c64scene-ar/llvm-6502.git
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69db8da023
1. Clean up the TargetMachine structure. No more wierd pointers that have to be cast around and taken care of by the target. 2. Instruction Scheduling now takes the schedinfo as an argument. The same should be done with the instinfo, it just isn't now. 3. Sparc.h is now just a factory method. Eventually this file will dissapear, but probably not until we have more than one backend. :) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@564 91177308-0d34-0410-b5e6-96231b3b80d8
73 lines
2.2 KiB
C++
73 lines
2.2 KiB
C++
// $Id$ -*- C++ -*-
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//***************************************************************************
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// File:
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// InstrScheduling.h
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//
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// Purpose:
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//
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// History:
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// 7/23/01 - Vikram Adve - Created
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//***************************************************************************
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#ifndef LLVM_CODEGEN_INSTR_SCHEDULING_H
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#define LLVM_CODEGEN_INSTR_SCHEDULING_H
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#include "llvm/Support/CommandLine.h"
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#include "llvm/CodeGen/MachineInstr.h"
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class Method;
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class SchedulingManager;
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class TargetMachine;
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class MachineSchedInfo;
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// Debug option levels for instruction scheduling
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enum SchedDebugLevel_t {
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Sched_NoDebugInfo,
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Sched_PrintMachineCode,
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Sched_PrintSchedTrace,
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Sched_PrintSchedGraphs,
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};
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extern cl::Enum<SchedDebugLevel_t> SchedDebugLevel;
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//---------------------------------------------------------------------------
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// Function: ScheduleInstructionsWithSSA
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//
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// Purpose:
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// Entry point for instruction scheduling on SSA form.
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// Schedules the machine instructions generated by instruction selection.
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// Assumes that register allocation has not been done, i.e., operands
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// are still in SSA form.
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//---------------------------------------------------------------------------
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bool ScheduleInstructionsWithSSA(Method* method, const TargetMachine &Target,
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const MachineSchedInfo &schedInfo);
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//---------------------------------------------------------------------------
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// Function: ScheduleInstructions
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//
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// Purpose:
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// Entry point for instruction scheduling on machine code.
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// Schedules the machine instructions generated by instruction selection.
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// Assumes that register allocation has been done.
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//---------------------------------------------------------------------------
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// Not implemented yet.
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bool ScheduleInstructions (Method* method,
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const TargetMachine &Target);
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//---------------------------------------------------------------------------
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// Function: instrIsFeasible
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//
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// Purpose:
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// Used by the priority analysis to filter out instructions
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// that are not feasible to issue in the current cycle.
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// Should only be used during schedule construction..
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//---------------------------------------------------------------------------
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bool instrIsFeasible (const SchedulingManager& S,
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MachineOpCode opCode);
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#endif
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