mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-10-31 09:11:13 +00:00
69db8da023
1. Clean up the TargetMachine structure. No more wierd pointers that have to be cast around and taken care of by the target. 2. Instruction Scheduling now takes the schedinfo as an argument. The same should be done with the instinfo, it just isn't now. 3. Sparc.h is now just a factory method. Eventually this file will dissapear, but probably not until we have more than one backend. :) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@564 91177308-0d34-0410-b5e6-96231b3b80d8
788 lines
24 KiB
C++
788 lines
24 KiB
C++
// $Id$ -*-c++-*-
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//***************************************************************************
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// File:
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// TargetMachine.h
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//
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// Purpose:
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//
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// History:
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// 7/12/01 - Vikram Adve - Created
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//**************************************************************************/
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#ifndef LLVM_CODEGEN_TARGETMACHINE_H
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#define LLVM_CODEGEN_TARGETMACHINE_H
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#include "llvm/CodeGen/TargetData.h"
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#include "llvm/Support/NonCopyable.h"
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#include "llvm/Support/DataTypes.h"
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#include <string>
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#include <hash_map>
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#include <hash_set>
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#include <algorithm>
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class StructType;
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struct MachineInstrDescriptor;
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class TargetMachine;
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//************************ Exported Data Types *****************************/
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//---------------------------------------------------------------------------
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// Data types used to define information about a single machine instruction
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//---------------------------------------------------------------------------
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typedef int MachineOpCode;
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typedef int OpCodeMask;
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typedef int InstrSchedClass;
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static const unsigned MAX_OPCODE_SIZE = 16;
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typedef long long cycles_t;
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const cycles_t HUGE_LATENCY = ~((unsigned long long) 1 << sizeof(cycles_t)-1);
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const cycles_t INVALID_LATENCY = -HUGE_LATENCY;
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class OpCodePair {
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public:
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long val; // make long by concatenating two opcodes
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OpCodePair(MachineOpCode op1, MachineOpCode op2)
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: val((op1 < 0 || op2 < 0)?
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-1 : (long)((((unsigned) op1) << MAX_OPCODE_SIZE) | (unsigned) op2)) {}
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bool operator==(const OpCodePair& op) const {
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return val == op.val;
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}
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private:
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OpCodePair(); // disable for now
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};
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template <> struct hash<OpCodePair> {
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size_t operator()(const OpCodePair& pair) const {
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return hash<long>()(pair.val);
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}
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};
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// Global variable holding an array of descriptors for machine instructions.
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// The actual object needs to be created separately for each target machine.
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// This variable is initialized and reset by class MachineInstrInfo.
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//
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extern const MachineInstrDescriptor* TargetInstrDescriptors;
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//---------------------------------------------------------------------------
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// struct MachineInstrDescriptor:
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// Predefined information about each machine instruction.
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// Designed to initialized statically.
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//
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// class MachineInstructionInfo
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// Interface to description of machine instructions
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//
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//---------------------------------------------------------------------------
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const unsigned int M_NOP_FLAG = 1;
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const unsigned int M_BRANCH_FLAG = 1 << 1;
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const unsigned int M_CALL_FLAG = 1 << 2;
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const unsigned int M_RET_FLAG = 1 << 3;
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const unsigned int M_ARITH_FLAG = 1 << 4;
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const unsigned int M_CC_FLAG = 1 << 6;
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const unsigned int M_LOGICAL_FLAG = 1 << 6;
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const unsigned int M_INT_FLAG = 1 << 7;
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const unsigned int M_FLOAT_FLAG = 1 << 8;
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const unsigned int M_CONDL_FLAG = 1 << 9;
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const unsigned int M_LOAD_FLAG = 1 << 10;
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const unsigned int M_PREFETCH_FLAG = 1 << 11;
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const unsigned int M_STORE_FLAG = 1 << 12;
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const unsigned int M_DUMMY_PHI_FLAG = 1 << 13;
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struct MachineInstrDescriptor {
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string opCodeString; // Assembly language mnemonic for the opcode.
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int numOperands; // Number of args; -1 if variable #args
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int resultPos; // Position of the result; -1 if no result
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unsigned int maxImmedConst; // Largest +ve constant in IMMMED field or 0.
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bool immedIsSignExtended; // Is IMMED field sign-extended? If so,
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// smallest -ve value is -(maxImmedConst+1).
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unsigned int numDelaySlots; // Number of delay slots after instruction
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unsigned int latency; // Latency in machine cycles
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InstrSchedClass schedClass; // enum identifying instr sched class
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unsigned int iclass; // flags identifying machine instr class
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};
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class MachineInstrInfo : public NonCopyableV {
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protected:
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const MachineInstrDescriptor* desc; // raw array to allow static init'n
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unsigned int descSize; // number of entries in the desc array
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unsigned int numRealOpCodes; // number of non-dummy op codes
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public:
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/*ctor*/ MachineInstrInfo(const MachineInstrDescriptor* _desc,
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unsigned int _descSize,
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unsigned int _numRealOpCodes);
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/*dtor*/ virtual ~MachineInstrInfo();
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unsigned int getNumRealOpCodes() const {
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return numRealOpCodes;
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}
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unsigned int getNumTotalOpCodes() const {
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return descSize;
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}
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const MachineInstrDescriptor& getDescriptor(MachineOpCode opCode) const {
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assert(opCode >= 0 && opCode < (int) descSize);
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return desc[opCode];
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}
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int getNumOperands (MachineOpCode opCode) const {
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return getDescriptor(opCode).numOperands;
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}
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int getResultPos (MachineOpCode opCode) const {
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return getDescriptor(opCode).resultPos;
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}
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unsigned int getNumDelaySlots(MachineOpCode opCode) const {
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return getDescriptor(opCode).numDelaySlots;
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}
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InstrSchedClass getSchedClass (MachineOpCode opCode) const {
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return getDescriptor(opCode).schedClass;
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}
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//
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// Query instruction class flags according to the machine-independent
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// flags listed above.
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//
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unsigned int getIClass (MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass;
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}
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bool isNop (MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_NOP_FLAG;
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}
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bool isBranch (MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_BRANCH_FLAG;
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}
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bool isCall (MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_CALL_FLAG;
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}
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bool isReturn (MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_RET_FLAG;
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}
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bool isControlFlow (MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_BRANCH_FLAG
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|| getDescriptor(opCode).iclass & M_CALL_FLAG
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|| getDescriptor(opCode).iclass & M_RET_FLAG;
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}
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bool isArith (MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_RET_FLAG;
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}
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bool isCCInstr (MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_CC_FLAG;
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}
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bool isLogical (MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_LOGICAL_FLAG;
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}
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bool isIntInstr (MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_INT_FLAG;
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}
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bool isFloatInstr (MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_FLOAT_FLAG;
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}
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bool isConditional (MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_CONDL_FLAG;
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}
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bool isLoad (MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_LOAD_FLAG;
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}
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bool isPrefetch (MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_PREFETCH_FLAG;
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}
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bool isLoadOrPrefetch (MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_LOAD_FLAG
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|| getDescriptor(opCode).iclass & M_PREFETCH_FLAG;
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}
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bool isStore (MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_STORE_FLAG;
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}
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bool isMemoryAccess (MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_LOAD_FLAG
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|| getDescriptor(opCode).iclass & M_PREFETCH_FLAG
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|| getDescriptor(opCode).iclass & M_STORE_FLAG;
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}
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bool isDummyPhiInstr (MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_DUMMY_PHI_FLAG;
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}
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// delete this later *******
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bool isPhi(MachineOpCode opCode) { return isDummyPhiInstr(opCode); }
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// Check if an instruction can be issued before its operands are ready,
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// or if a subsequent instruction that uses its result can be issued
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// before the results are ready.
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// Default to true since most instructions on many architectures allow this.
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//
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virtual bool hasOperandInterlock(MachineOpCode opCode) const {
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return true;
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}
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virtual bool hasResultInterlock(MachineOpCode opCode) const {
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return true;
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}
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//
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// Latencies for individual instructions and instruction pairs
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//
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virtual int minLatency (MachineOpCode opCode) const {
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return getDescriptor(opCode).latency;
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}
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virtual int maxLatency (MachineOpCode opCode) const {
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return getDescriptor(opCode).latency;
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}
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// Check if the specified constant fits in the immediate field
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// of this machine instruction
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//
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virtual bool constantFitsInImmedField(MachineOpCode opCode,
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int64_t intValue) const;
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// Return the largest +ve constant that can be held in the IMMMED field
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// of this machine instruction.
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// isSignExtended is set to true if the value is sign-extended before use
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// (this is true for all immediate fields in SPARC instructions).
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// Return 0 if the instruction has no IMMED field.
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//
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virtual uint64_t maxImmedConstant(MachineOpCode opCode,
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bool& isSignExtended) const {
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isSignExtended = getDescriptor(opCode).immedIsSignExtended;
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return getDescriptor(opCode).maxImmedConst;
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}
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};
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//---------------------------------------------------------------------------
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// class MachineResource
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// class CPUResource
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//
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// Purpose:
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// Representation of a single machine resource used in specifying
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// resource usages of machine instructions for scheduling.
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//---------------------------------------------------------------------------
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typedef unsigned int resourceId_t;
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class MachineResource {
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public:
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const string rname;
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resourceId_t rid;
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/*ctor*/ MachineResource(const string& resourceName)
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: rname(resourceName), rid(nextId++) {}
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private:
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static resourceId_t nextId;
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MachineResource(); // disable
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};
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class CPUResource : public MachineResource {
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public:
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int maxNumUsers; // MAXINT if no restriction
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/*ctor*/ CPUResource(const string& rname, int maxUsers)
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: MachineResource(rname), maxNumUsers(maxUsers) {}
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};
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//---------------------------------------------------------------------------
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// struct InstrClassRUsage
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// struct InstrRUsageDelta
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// struct InstrIssueDelta
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// struct InstrRUsage
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//
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// Purpose:
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// The first three are structures used to specify machine resource
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// usages for each instruction in a machine description file:
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// InstrClassRUsage : resource usages common to all instrs. in a class
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// InstrRUsageDelta : add/delete resource usage for individual instrs.
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// InstrIssueDelta : add/delete instr. issue info for individual instrs
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//
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// The last one (InstrRUsage) is the internal representation of
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// instruction resource usage constructed from the above three.
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//---------------------------------------------------------------------------
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const int MAX_NUM_SLOTS = 32;
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const int MAX_NUM_CYCLES = 32;
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struct InstrClassRUsage {
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InstrSchedClass schedClass;
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int totCycles;
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// Issue restrictions common to instructions in this class
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unsigned int maxNumIssue;
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bool isSingleIssue;
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bool breaksGroup;
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cycles_t numBubbles;
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// Feasible slots to use for instructions in this class.
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// The size of vector S[] is `numSlots'.
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unsigned int numSlots;
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unsigned int feasibleSlots[MAX_NUM_SLOTS];
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// Resource usages common to instructions in this class.
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// The size of vector V[] is `numRUEntries'.
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unsigned int numRUEntries;
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struct {
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resourceId_t resourceId;
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unsigned int startCycle;
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int numCycles;
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} V[MAX_NUM_CYCLES];
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};
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struct InstrRUsageDelta {
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MachineOpCode opCode;
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resourceId_t resourceId;
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unsigned int startCycle;
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int numCycles;
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};
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// Specify instruction issue restrictions for individual instructions
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// that differ from the common rules for the class.
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//
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struct InstrIssueDelta {
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MachineOpCode opCode;
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bool isSingleIssue;
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bool breaksGroup;
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cycles_t numBubbles;
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};
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struct InstrRUsage {
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/*ctor*/ InstrRUsage () {}
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/*ctor*/ InstrRUsage (const InstrRUsage& instrRU);
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InstrRUsage& operator= (const InstrRUsage& instrRU);
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bool sameAsClass;
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// Issue restrictions for this instruction
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bool isSingleIssue;
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bool breaksGroup;
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cycles_t numBubbles;
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// Feasible slots to use for this instruction.
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vector<bool> feasibleSlots;
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// Resource usages for this instruction, with one resource vector per cycle.
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cycles_t numCycles;
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vector<vector<resourceId_t> > resourcesByCycle;
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private:
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// Conveniences for initializing this structure
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InstrRUsage& operator= (const InstrClassRUsage& classRU);
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void addIssueDelta (const InstrIssueDelta& delta);
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void addUsageDelta (const InstrRUsageDelta& delta);
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void setMaxSlots (int maxNumSlots);
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friend class MachineSchedInfo; // give access to these functions
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};
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inline void
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InstrRUsage::setMaxSlots(int maxNumSlots)
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{
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feasibleSlots.resize(maxNumSlots);
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}
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inline InstrRUsage&
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InstrRUsage::operator=(const InstrRUsage& instrRU)
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{
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sameAsClass = instrRU.sameAsClass;
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isSingleIssue = instrRU.isSingleIssue;
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breaksGroup = instrRU.breaksGroup;
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numBubbles = instrRU.numBubbles;
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feasibleSlots = instrRU.feasibleSlots;
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numCycles = instrRU.numCycles;
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resourcesByCycle = instrRU.resourcesByCycle;
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return *this;
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}
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inline /*ctor*/
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InstrRUsage::InstrRUsage(const InstrRUsage& instrRU)
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{
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*this = instrRU;
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}
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inline InstrRUsage&
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InstrRUsage::operator=(const InstrClassRUsage& classRU)
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{
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sameAsClass = true;
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isSingleIssue = classRU.isSingleIssue;
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breaksGroup = classRU.breaksGroup;
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numBubbles = classRU.numBubbles;
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for (unsigned i=0; i < classRU.numSlots; i++)
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{
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unsigned slot = classRU.feasibleSlots[i];
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assert(slot < feasibleSlots.size() && "Invalid slot specified!");
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this->feasibleSlots[slot] = true;
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}
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this->numCycles = classRU.totCycles;
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this->resourcesByCycle.resize(this->numCycles);
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for (unsigned i=0; i < classRU.numRUEntries; i++)
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for (unsigned c=classRU.V[i].startCycle, NC = c + classRU.V[i].numCycles;
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c < NC; c++)
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this->resourcesByCycle[c].push_back(classRU.V[i].resourceId);
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// Sort each resource usage vector by resourceId_t to speed up conflict checking
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for (unsigned i=0; i < this->resourcesByCycle.size(); i++)
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sort(resourcesByCycle[i].begin(), resourcesByCycle[i].end());
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return *this;
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}
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inline void
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InstrRUsage::addIssueDelta(const InstrIssueDelta& delta)
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{
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sameAsClass = false;
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isSingleIssue = delta.isSingleIssue;
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breaksGroup = delta.breaksGroup;
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numBubbles = delta.numBubbles;
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}
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// Add the extra resource usage requirements specified in the delta.
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// Note that a negative value of `numCycles' means one entry for that
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// resource should be deleted for each cycle.
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//
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inline void
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InstrRUsage::addUsageDelta(const InstrRUsageDelta& delta)
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{
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int NC = delta.numCycles;
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this->sameAsClass = false;
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// resize the resources vector if more cycles are specified
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unsigned maxCycles = this->numCycles;
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maxCycles = max(maxCycles, delta.startCycle + abs(NC) - 1);
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if (maxCycles > this->numCycles)
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{
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this->resourcesByCycle.resize(maxCycles);
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this->numCycles = maxCycles;
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}
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if (NC >= 0)
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for (unsigned c=delta.startCycle, last=c+NC-1; c <= last; c++)
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this->resourcesByCycle[c].push_back(delta.resourceId);
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else
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// Remove the resource from all NC cycles.
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for (unsigned c=delta.startCycle, last=(c-NC)-1; c <= last; c++)
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{
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// Look for the resource backwards so we remove the last entry
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// for that resource in each cycle.
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vector<resourceId_t>& rvec = this->resourcesByCycle[c];
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int r;
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for (r = (int) rvec.size(); r >= 0; r--)
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if (rvec[r] == delta.resourceId)
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{// found last entry for the resource
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rvec.erase(rvec.begin() + r);
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break;
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}
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assert(r >= 0 && "Resource to remove was unused in cycle c!");
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}
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}
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//---------------------------------------------------------------------------
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// class MachineSchedInfo
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//
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// Purpose:
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// Common interface to machine information for instruction scheduling
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//---------------------------------------------------------------------------
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class MachineSchedInfo : public NonCopyableV {
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public:
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unsigned int maxNumIssueTotal;
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int longestIssueConflict;
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int branchMispredictPenalty; // 4 for SPARC IIi
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int branchTargetUnknownPenalty; // 2 for SPARC IIi
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int l1DCacheMissPenalty; // 7 or 9 for SPARC IIi
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int l1ICacheMissPenalty; // ? for SPARC IIi
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bool inOrderLoads ; // true for SPARC IIi
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bool inOrderIssue; // true for SPARC IIi
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bool inOrderExec; // false for most architectures
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bool inOrderRetire; // true for most architectures
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protected:
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inline const InstrRUsage& getInstrRUsage(MachineOpCode opCode) const {
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assert(opCode >= 0 && opCode < (int) instrRUsages.size());
|
|
return instrRUsages[opCode];
|
|
}
|
|
inline const InstrClassRUsage&
|
|
getClassRUsage(const InstrSchedClass& sc) const {
|
|
assert(sc >= 0 && sc < numSchedClasses);
|
|
return classRUsages[sc];
|
|
}
|
|
|
|
public:
|
|
/*ctor*/ MachineSchedInfo (int _numSchedClasses,
|
|
const MachineInstrInfo* _mii,
|
|
const InstrClassRUsage* _classRUsages,
|
|
const InstrRUsageDelta* _usageDeltas,
|
|
const InstrIssueDelta* _issueDeltas,
|
|
unsigned int _numUsageDeltas,
|
|
unsigned int _numIssueDeltas);
|
|
/*dtor*/ virtual ~MachineSchedInfo () {}
|
|
|
|
inline const MachineInstrInfo& getInstrInfo() const {
|
|
return *mii;
|
|
}
|
|
|
|
inline int getNumSchedClasses() const {
|
|
return numSchedClasses;
|
|
}
|
|
|
|
inline unsigned int getMaxNumIssueTotal() const {
|
|
return maxNumIssueTotal;
|
|
}
|
|
|
|
inline unsigned int getMaxIssueForClass(const InstrSchedClass& sc) const {
|
|
assert(sc >= 0 && sc < numSchedClasses);
|
|
return classRUsages[sc].maxNumIssue;
|
|
}
|
|
|
|
inline InstrSchedClass getSchedClass (MachineOpCode opCode) const {
|
|
return getInstrInfo().getSchedClass(opCode);
|
|
}
|
|
|
|
inline bool instrCanUseSlot (MachineOpCode opCode,
|
|
unsigned s) const {
|
|
assert(s < getInstrRUsage(opCode).feasibleSlots.size() && "Invalid slot!");
|
|
return getInstrRUsage(opCode).feasibleSlots[s];
|
|
}
|
|
|
|
inline int getLongestIssueConflict () const {
|
|
return longestIssueConflict;
|
|
}
|
|
|
|
inline int getMinIssueGap (MachineOpCode fromOp,
|
|
MachineOpCode toOp) const {
|
|
hash_map<OpCodePair,int>::const_iterator
|
|
I = issueGaps.find(OpCodePair(fromOp, toOp));
|
|
return (I == issueGaps.end())? 0 : (*I).second;
|
|
}
|
|
|
|
inline const vector<MachineOpCode>*
|
|
getConflictList(MachineOpCode opCode) const {
|
|
hash_map<MachineOpCode,vector<MachineOpCode> >::const_iterator
|
|
I = conflictLists.find(opCode);
|
|
return (I == conflictLists.end())? NULL : & (*I).second;
|
|
}
|
|
|
|
inline bool isSingleIssue (MachineOpCode opCode) const {
|
|
return getInstrRUsage(opCode).isSingleIssue;
|
|
}
|
|
|
|
inline bool breaksIssueGroup (MachineOpCode opCode) const {
|
|
return getInstrRUsage(opCode).breaksGroup;
|
|
}
|
|
|
|
inline unsigned int numBubblesAfter (MachineOpCode opCode) const {
|
|
return getInstrRUsage(opCode).numBubbles;
|
|
}
|
|
|
|
protected:
|
|
virtual void initializeResources ();
|
|
|
|
private:
|
|
void computeInstrResources(const vector<InstrRUsage>& instrRUForClasses);
|
|
void computeIssueGaps(const vector<InstrRUsage>& instrRUForClasses);
|
|
|
|
protected:
|
|
int numSchedClasses;
|
|
const MachineInstrInfo* mii;
|
|
const InstrClassRUsage* classRUsages; // raw array by sclass
|
|
const InstrRUsageDelta* usageDeltas; // raw array [1:numUsageDeltas]
|
|
const InstrIssueDelta* issueDeltas; // raw array [1:numIssueDeltas]
|
|
unsigned int numUsageDeltas;
|
|
unsigned int numIssueDeltas;
|
|
|
|
vector<InstrRUsage> instrRUsages; // indexed by opcode
|
|
hash_map<OpCodePair,int> issueGaps; // indexed by opcode pair
|
|
hash_map<MachineOpCode,vector<MachineOpCode> >
|
|
conflictLists; // indexed by opcode
|
|
};
|
|
|
|
|
|
|
|
//-----------------------------------------------------------------------------
|
|
// class MachineRegClassInfo
|
|
//
|
|
// Purpose:
|
|
// Interface to description of machine register class (e.g., int reg class
|
|
// float reg class etc)
|
|
//
|
|
//--------------------------------------------------------------------------
|
|
|
|
class IGNode;
|
|
|
|
|
|
class MachineRegClassInfo {
|
|
|
|
protected:
|
|
|
|
const unsigned RegClassID; // integer ID of a reg class
|
|
const unsigned NumOfAvailRegs; // # of avail for coloring -without SP etc.
|
|
const unsigned NumOfAllRegs; // # of all registers -including SP,g0 etc.
|
|
|
|
public:
|
|
|
|
inline unsigned getRegClassID() const { return RegClassID; }
|
|
inline unsigned getNumOfAvailRegs() const { return NumOfAvailRegs; }
|
|
inline unsigned getNumOfAllRegs() const { return NumOfAllRegs; }
|
|
|
|
|
|
|
|
// This method should find a color which is not used by neighbors
|
|
// (i.e., a false position in IsColorUsedArr) and
|
|
virtual void colorIGNode(IGNode * Node, bool IsColorUsedArr[] ) const = 0;
|
|
|
|
|
|
MachineRegClassInfo(const unsigned ID, const unsigned NVR,
|
|
const unsigned NAR): RegClassID(ID), NumOfAvailRegs(NVR),
|
|
NumOfAllRegs(NAR)
|
|
{ } // empty constructor
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
//---------------------------------------------------------------------------
|
|
// class MachineRegInfo
|
|
//
|
|
// Purpose:
|
|
// Interface to register info of target machine
|
|
//
|
|
//--------------------------------------------------------------------------
|
|
|
|
class LiveRangeInfo;
|
|
class Method;
|
|
class Instruction;
|
|
class LiveRange;
|
|
class AddedInstrns;
|
|
class MachineInstr;
|
|
typedef hash_map<const MachineInstr *, AddedInstrns *> AddedInstrMapType;
|
|
|
|
// A vector of all machine register classes
|
|
typedef vector<const MachineRegClassInfo *> MachineRegClassArrayType;
|
|
|
|
|
|
class MachineRegInfo : public NonCopyableV {
|
|
|
|
protected:
|
|
|
|
MachineRegClassArrayType MachineRegClassArr;
|
|
|
|
|
|
public:
|
|
|
|
|
|
inline unsigned int getNumOfRegClasses() const {
|
|
return MachineRegClassArr.size();
|
|
}
|
|
|
|
const MachineRegClassInfo *const getMachineRegClass(unsigned i) const {
|
|
return MachineRegClassArr[i];
|
|
}
|
|
|
|
|
|
virtual unsigned getRegClassIDOfValue (const Value *const Val) const = 0;
|
|
|
|
virtual void colorArgs(const Method *const Meth,
|
|
LiveRangeInfo & LRI) const = 0;
|
|
|
|
virtual void colorCallArgs(vector<const Instruction *> & CallInstrList,
|
|
LiveRangeInfo& LRI,
|
|
AddedInstrMapType& AddedInstrMap ) const = 0 ;
|
|
|
|
virtual int getUnifiedRegNum(int RegClassID, int reg) const = 0;
|
|
|
|
virtual const string getUnifiedRegName(int reg) const = 0;
|
|
|
|
//virtual void printReg(const LiveRange *const LR) const =0;
|
|
|
|
MachineRegInfo() { }
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
//---------------------------------------------------------------------------
|
|
// class TargetMachine
|
|
//
|
|
// Purpose:
|
|
// Primary interface to machine description for the target machine.
|
|
//
|
|
//---------------------------------------------------------------------------
|
|
|
|
class TargetMachine : public NonCopyableV {
|
|
public:
|
|
const string TargetName;
|
|
const TargetData DataLayout; // Calculates type size & alignment
|
|
int optSizeForSubWordData;
|
|
int minMemOpWordSize;
|
|
int maxAtomicMemOpWordSize;
|
|
|
|
// Register information. This needs to be reorganized into a single class.
|
|
int zeroRegNum; // register that gives 0 if any (-1 if none)
|
|
|
|
public:
|
|
TargetMachine(const string &targetname,
|
|
unsigned char PtrSize = 8, unsigned char PtrAl = 8,
|
|
unsigned char DoubleAl = 8, unsigned char FloatAl = 4,
|
|
unsigned char LongAl = 8, unsigned char IntAl = 4,
|
|
unsigned char ShortAl = 2, unsigned char ByteAl = 1)
|
|
: TargetName(targetname), DataLayout(targetname, PtrSize, PtrAl,
|
|
DoubleAl, FloatAl, LongAl, IntAl,
|
|
ShortAl, ByteAl) { }
|
|
virtual ~TargetMachine() {}
|
|
|
|
virtual const MachineInstrInfo& getInstrInfo() const = 0;
|
|
|
|
virtual unsigned int findOptimalStorageSize (const Type* ty) const;
|
|
|
|
// This really should be in the register info class
|
|
virtual bool regsMayBeAliased (unsigned int regNum1,
|
|
unsigned int regNum2) const {
|
|
return (regNum1 == regNum2);
|
|
}
|
|
|
|
// compileMethod - This does everything neccesary to compile a method into the
|
|
// built in representation. This allows the target to have complete control
|
|
// over how it does compilation. This does not emit assembly or output
|
|
// machine code however, this is done later.
|
|
//
|
|
virtual bool compileMethod(Method *M) = 0;
|
|
|
|
// emitAssembly - Output assembly language code (a .s file) for the specified
|
|
// method. The specified method must have been compiled before this may be
|
|
// used.
|
|
//
|
|
virtual void emitAssembly(Method *M, ostream &OutStr) { /* todo */ }
|
|
};
|
|
|
|
#endif
|