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https://github.com/c64scene-ar/llvm-6502.git
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f28987b76e
This simplifies many of the target description files since it is common for register classes to be related or contain sequences of numbered registers. I have verified that this doesn't change the files generated by TableGen for ARM and X86. It alters the allocation order of MBlaze GPR and Mips FGR32 registers, but I believe the change is benign. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133105 91177308-0d34-0410-b5e6-96231b3b80d8
86 lines
2.9 KiB
TableGen
86 lines
2.9 KiB
TableGen
//===- MSP430RegisterInfo.td - MSP430 Register defs ----------*- tblgen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Declarations that describe the MSP430 register file
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//===----------------------------------------------------------------------===//
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class MSP430Reg<bits<4> num, string n> : Register<n> {
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field bits<4> Num = num;
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let Namespace = "MSP430";
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}
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class MSP430RegWithSubregs<bits<4> num, string n, list<Register> subregs>
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: RegisterWithSubRegs<n, subregs> {
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field bits<4> Num = num;
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let Namespace = "MSP430";
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}
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//===----------------------------------------------------------------------===//
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// Registers
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//===----------------------------------------------------------------------===//
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def PCB : MSP430Reg<0, "r0">;
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def SPB : MSP430Reg<1, "r1">;
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def SRB : MSP430Reg<2, "r2">;
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def CGB : MSP430Reg<3, "r3">;
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def FPB : MSP430Reg<4, "r4">;
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def R5B : MSP430Reg<5, "r5">;
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def R6B : MSP430Reg<6, "r6">;
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def R7B : MSP430Reg<7, "r7">;
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def R8B : MSP430Reg<8, "r8">;
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def R9B : MSP430Reg<9, "r9">;
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def R10B : MSP430Reg<10, "r10">;
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def R11B : MSP430Reg<11, "r11">;
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def R12B : MSP430Reg<12, "r12">;
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def R13B : MSP430Reg<13, "r13">;
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def R14B : MSP430Reg<14, "r14">;
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def R15B : MSP430Reg<15, "r15">;
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def subreg_8bit : SubRegIndex { let Namespace = "MSP430"; }
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let SubRegIndices = [subreg_8bit] in {
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def PCW : MSP430RegWithSubregs<0, "r0", [PCB]>;
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def SPW : MSP430RegWithSubregs<1, "r1", [SPB]>;
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def SRW : MSP430RegWithSubregs<2, "r2", [SRB]>;
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def CGW : MSP430RegWithSubregs<3, "r3", [CGB]>;
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def FPW : MSP430RegWithSubregs<4, "r4", [FPB]>;
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def R5W : MSP430RegWithSubregs<5, "r5", [R5B]>;
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def R6W : MSP430RegWithSubregs<6, "r6", [R6B]>;
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def R7W : MSP430RegWithSubregs<7, "r7", [R7B]>;
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def R8W : MSP430RegWithSubregs<8, "r8", [R8B]>;
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def R9W : MSP430RegWithSubregs<9, "r9", [R9B]>;
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def R10W : MSP430RegWithSubregs<10, "r10", [R10B]>;
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def R11W : MSP430RegWithSubregs<11, "r11", [R11B]>;
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def R12W : MSP430RegWithSubregs<12, "r12", [R12B]>;
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def R13W : MSP430RegWithSubregs<13, "r13", [R13B]>;
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def R14W : MSP430RegWithSubregs<14, "r14", [R14B]>;
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def R15W : MSP430RegWithSubregs<15, "r15", [R15B]>;
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}
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def GR8 : RegisterClass<"MSP430", [i8], 8,
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// Volatile registers
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(add R12B, R13B, R14B, R15B, R11B, R10B, R9B, R8B, R7B, R6B, R5B,
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// Frame pointer, sometimes allocable
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FPB,
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// Volatile, but not allocable
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PCB, SPB, SRB, CGB)>;
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def GR16 : RegisterClass<"MSP430", [i16], 16,
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// Volatile registers
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(add R12W, R13W, R14W, R15W, R11W, R10W, R9W, R8W, R7W, R6W, R5W,
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// Frame pointer, sometimes allocable
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FPW,
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// Volatile, but not allocable
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PCW, SPW, SRW, CGW)>
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{
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let SubRegClasses = [(GR8 subreg_8bit)];
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}
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