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https://github.com/c64scene-ar/llvm-6502.git
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30fc5bbfd1
beneficial cases. See the changes in test/CodeGen/X86/tail-opts.ll and test/CodeGen/ARM/ifcvt2.ll for details. The fix is to change HashEndOfMBB to hash at most one instruction, instead of trying to apply heuristics about when it will be profitable to consider more than one instruction. The regular tail-merging heuristics are already prepared to handle the same cases, and they're more precise. Also, make test/CodeGen/ARM/ifcvt5.ll and test/CodeGen/Thumb2/thumb2-branch.ll slightly more complex so that they continue to test what they're intended to test. And, this eliminates the problem in test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll, the testcase from PR5204. Update it accordingly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102907 91177308-0d34-0410-b5e6-96231b3b80d8
38 lines
835 B
LLVM
38 lines
835 B
LLVM
; RUN: llc < %s -march=arm > %t
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; RUN: grep bxlt %t | count 1
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; RUN: grep bxgt %t | count 1
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; RUN: not grep bxge %t
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; RUN: not grep bxle %t
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define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) {
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%tmp2 = icmp sgt i32 %c, 10
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%tmp5 = icmp slt i32 %d, 4
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%tmp8 = or i1 %tmp5, %tmp2
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%tmp13 = add i32 %b, %a
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br i1 %tmp8, label %cond_true, label %UnifiedReturnBlock
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cond_true:
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%tmp15 = add i32 %tmp13, %c
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%tmp1821 = sub i32 %tmp15, %d
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ret i32 %tmp1821
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UnifiedReturnBlock:
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ret i32 %tmp13
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}
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define i32 @t2(i32 %a, i32 %b, i32 %c, i32 %d) {
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%tmp2 = icmp sgt i32 %c, 10
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%tmp5 = icmp slt i32 %d, 4
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%tmp8 = and i1 %tmp5, %tmp2
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%tmp13 = add i32 %b, %a
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br i1 %tmp8, label %cond_true, label %UnifiedReturnBlock
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cond_true:
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%tmp15 = add i32 %tmp13, %c
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%tmp1821 = sub i32 %tmp15, %d
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ret i32 %tmp1821
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UnifiedReturnBlock:
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ret i32 %tmp13
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}
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