mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-21 03:29:40 +00:00
is zero. This lets the register allocator elide some copies in some cases. This implements CodeGen/PowerPC/rlwimi-commute.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23292 91177308-0d34-0410-b5e6-96231b3b80d8
61 lines
2.0 KiB
C++
61 lines
2.0 KiB
C++
//===- PPC32InstrInfo.h - PowerPC32 Instruction Information -----*- C++ -*-===//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file was developed by the LLVM research group and is distributed under
|
|
// the University of Illinois Open Source License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
// This file contains the PowerPC implementation of the TargetInstrInfo class.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
#ifndef POWERPC32_INSTRUCTIONINFO_H
|
|
#define POWERPC32_INSTRUCTIONINFO_H
|
|
|
|
#include "PowerPCInstrInfo.h"
|
|
#include "PPC32RegisterInfo.h"
|
|
|
|
namespace llvm {
|
|
|
|
class PPC32InstrInfo : public TargetInstrInfo {
|
|
const PPC32RegisterInfo RI;
|
|
public:
|
|
PPC32InstrInfo();
|
|
|
|
/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
|
|
/// such, whenever a client has an instance of instruction info, it should
|
|
/// always be able to get register info as well (through this method).
|
|
///
|
|
virtual const MRegisterInfo &getRegisterInfo() const { return RI; }
|
|
|
|
//
|
|
// Return true if the instruction is a register to register move and
|
|
// leave the source and dest operands in the passed parameters.
|
|
//
|
|
virtual bool isMoveInstr(const MachineInstr& MI,
|
|
unsigned& sourceReg,
|
|
unsigned& destReg) const;
|
|
|
|
// commuteInstruction - We can commute rlwimi instructions, but only if the
|
|
// rotate amt is zero. We also have to munge the immediates a bit.
|
|
virtual MachineInstr *commuteInstruction(MachineInstr *MI) const;
|
|
|
|
static unsigned invertPPCBranchOpcode(unsigned Opcode) {
|
|
switch (Opcode) {
|
|
default: assert(0 && "Unknown PPC branch opcode!");
|
|
case PPC::BEQ: return PPC::BNE;
|
|
case PPC::BNE: return PPC::BEQ;
|
|
case PPC::BLT: return PPC::BGE;
|
|
case PPC::BGE: return PPC::BLT;
|
|
case PPC::BGT: return PPC::BLE;
|
|
case PPC::BLE: return PPC::BGT;
|
|
}
|
|
}
|
|
};
|
|
|
|
}
|
|
|
|
#endif
|