Nick Lewycky 6a7df9aae6 Remove redundant getAnalysis<> calls in GlobalOpt. Add a few Itanium ABI calls ...

to TargetLibraryInfo and use one of them in GlobalOpt.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150323 91177308-0d34-0410-b5e6-96231b3b80d8

2012-02-12 02:15:20 +00:00

..

Mangler.h

…

Target.td

Specify SubRegIndex components on the index itself.

2012-02-01 23:16:41 +00:00

TargetCallingConv.h

Minimize #include's and forward-declares in Target.

2011-12-10 22:35:47 +00:00

TargetCallingConv.td

Add TableGen support for callee saved registers.

2012-01-17 22:46:58 +00:00

TargetData.h

Haven't yet found a nice way to handle TargetData verification in the

2011-10-20 19:24:44 +00:00

TargetELFWriterInfo.h

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TargetFrameLowering.h

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TargetInstrInfo.h

Convert assert(0) to llvm_unreachable

2012-02-05 22:14:15 +00:00

TargetIntrinsicInfo.h

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TargetJITInfo.h

Convert assert(0) to llvm_unreachable

2012-02-05 22:14:15 +00:00

TargetLibraryInfo.h

Remove redundant getAnalysis<> calls in GlobalOpt. Add a few Itanium ABI calls

2012-02-12 02:15:20 +00:00

TargetLowering.h

Convert assert(0) to llvm_unreachable

2012-02-05 22:14:15 +00:00

TargetLoweringObjectFile.h

Properly emit ctors / dtors with priorities into desired sections

2012-01-25 22:24:19 +00:00

TargetMachine.h

TargetPassConfig: confine the MC configuration to TargetMachine.

2012-02-04 02:56:59 +00:00

TargetOpcodes.h

First chunk of MachineInstr bundle support.

2011-12-06 22:12:01 +00:00

TargetOptions.h

RegAlloc superpass: includes phi elimination, coalescing, and scheduling.

2012-02-10 04:10:36 +00:00

TargetRegisterInfo.h

Store just the SimpleValueType in the generated VT tables for each register class, eliminating static ctors.

2012-02-09 12:35:37 +00:00

TargetSchedule.td

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TargetSelectionDAG.td

Initial CodeGen support for CTTZ/CTLZ where a zero input produces an

2011-12-13 01:56:10 +00:00

TargetSelectionDAGInfo.h

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TargetSubtargetInfo.h

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