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d410eaba04
test suite failures. The failures occur at each stage, and only get worse, so I'm reverting all of them. Please resubmit these patches, one at a time, after verifying that the regression test suite passes. Never submit a patch without running the regression test suite. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155372 91177308-0d34-0410-b5e6-96231b3b80d8
54 lines
1.9 KiB
TableGen
54 lines
1.9 KiB
TableGen
//===- HexagonSchedule.td - Hexagon Scheduling Definitions -*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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// Functional Units
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def LUNIT : FuncUnit;
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def LSUNIT : FuncUnit;
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def MUNIT : FuncUnit;
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def SUNIT : FuncUnit;
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// Itinerary classes
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def ALU32 : InstrItinClass;
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def ALU64 : InstrItinClass;
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def CR : InstrItinClass;
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def J : InstrItinClass;
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def JR : InstrItinClass;
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def LD : InstrItinClass;
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def M : InstrItinClass;
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def ST : InstrItinClass;
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def S : InstrItinClass;
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def PSEUDO : InstrItinClass;
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def HexagonItineraries :
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ProcessorItineraries<[LUNIT, LSUNIT, MUNIT, SUNIT], [], [
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InstrItinData<ALU32 , [InstrStage<1, [LUNIT, LSUNIT, MUNIT, SUNIT]>]>,
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InstrItinData<ALU64 , [InstrStage<1, [MUNIT, SUNIT]>]>,
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InstrItinData<CR , [InstrStage<1, [SUNIT]>]>,
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InstrItinData<J , [InstrStage<1, [SUNIT, MUNIT]>]>,
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InstrItinData<JR , [InstrStage<1, [MUNIT]>]>,
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InstrItinData<LD , [InstrStage<1, [LUNIT, LSUNIT]>]>,
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InstrItinData<M , [InstrStage<1, [MUNIT, SUNIT]>]>,
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InstrItinData<ST , [InstrStage<1, [LSUNIT]>]>,
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InstrItinData<S , [InstrStage<1, [SUNIT, MUNIT]>]>,
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InstrItinData<PSEUDO , [InstrStage<1, [LUNIT, LSUNIT, MUNIT, SUNIT]>]>
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]>;
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//===----------------------------------------------------------------------===//
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// V4 Machine Info +
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//===----------------------------------------------------------------------===//
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include "HexagonScheduleV4.td"
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//===----------------------------------------------------------------------===//
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// V4 Machine Info -
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//===----------------------------------------------------------------------===//
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