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https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152001 91177308-0d34-0410-b5e6-96231b3b80d8
254 lines
7.5 KiB
C++
254 lines
7.5 KiB
C++
//===-- DelaySlotFiller.cpp - Mips Delay Slot Filler ----------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Simple pass to fills delay slots with useful instructions.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "delay-slot-filler"
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#include "Mips.h"
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#include "MipsTargetMachine.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/ADT/Statistic.h"
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using namespace llvm;
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STATISTIC(FilledSlots, "Number of delay slots filled");
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STATISTIC(UsefulSlots, "Number of delay slots filled with instructions that"
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" are not NOP.");
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static cl::opt<bool> EnableDelaySlotFiller(
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"enable-mips-delay-filler",
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cl::init(false),
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cl::desc("Fill the Mips delay slots useful instructions."),
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cl::Hidden);
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namespace {
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struct Filler : public MachineFunctionPass {
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TargetMachine &TM;
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const TargetInstrInfo *TII;
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MachineBasicBlock::iterator LastFiller;
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static char ID;
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Filler(TargetMachine &tm)
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: MachineFunctionPass(ID), TM(tm), TII(tm.getInstrInfo()) { }
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virtual const char *getPassName() const {
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return "Mips Delay Slot Filler";
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}
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bool runOnMachineBasicBlock(MachineBasicBlock &MBB);
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bool runOnMachineFunction(MachineFunction &F) {
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bool Changed = false;
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for (MachineFunction::iterator FI = F.begin(), FE = F.end();
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FI != FE; ++FI)
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Changed |= runOnMachineBasicBlock(*FI);
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return Changed;
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}
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bool isDelayFiller(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator candidate);
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void insertCallUses(MachineBasicBlock::iterator MI,
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SmallSet<unsigned, 32>& RegDefs,
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SmallSet<unsigned, 32>& RegUses);
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void insertDefsUses(MachineBasicBlock::iterator MI,
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SmallSet<unsigned, 32>& RegDefs,
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SmallSet<unsigned, 32>& RegUses);
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bool IsRegInSet(SmallSet<unsigned, 32>& RegSet,
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unsigned Reg);
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bool delayHasHazard(MachineBasicBlock::iterator candidate,
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bool &sawLoad, bool &sawStore,
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SmallSet<unsigned, 32> &RegDefs,
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SmallSet<unsigned, 32> &RegUses);
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bool
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findDelayInstr(MachineBasicBlock &MBB, MachineBasicBlock::iterator slot,
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MachineBasicBlock::iterator &Filler);
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};
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char Filler::ID = 0;
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} // end of anonymous namespace
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/// runOnMachineBasicBlock - Fill in delay slots for the given basic block.
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/// We assume there is only one delay slot per delayed instruction.
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bool Filler::
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runOnMachineBasicBlock(MachineBasicBlock &MBB) {
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bool Changed = false;
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LastFiller = MBB.end();
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for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ++I)
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if (I->hasDelaySlot()) {
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++FilledSlots;
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Changed = true;
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MachineBasicBlock::iterator D;
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if (EnableDelaySlotFiller && findDelayInstr(MBB, I, D)) {
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MBB.splice(llvm::next(I), &MBB, D);
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++UsefulSlots;
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} else
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BuildMI(MBB, llvm::next(I), I->getDebugLoc(), TII->get(Mips::NOP));
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// Record the filler instruction that filled the delay slot.
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// The instruction after it will be visited in the next iteration.
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LastFiller = ++I;
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}
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return Changed;
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}
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/// createMipsDelaySlotFillerPass - Returns a pass that fills in delay
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/// slots in Mips MachineFunctions
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FunctionPass *llvm::createMipsDelaySlotFillerPass(MipsTargetMachine &tm) {
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return new Filler(tm);
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}
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bool Filler::findDelayInstr(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator slot,
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MachineBasicBlock::iterator &Filler) {
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SmallSet<unsigned, 32> RegDefs;
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SmallSet<unsigned, 32> RegUses;
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insertDefsUses(slot, RegDefs, RegUses);
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bool sawLoad = false;
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bool sawStore = false;
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for (MachineBasicBlock::reverse_iterator I(slot); I != MBB.rend(); ++I) {
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// skip debug value
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if (I->isDebugValue())
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continue;
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// Convert to forward iterator.
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MachineBasicBlock::iterator FI(llvm::next(I).base());
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if (I->hasUnmodeledSideEffects()
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|| I->isInlineAsm()
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|| I->isLabel()
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|| FI == LastFiller
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|| I->isPseudo()
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//
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// Should not allow:
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// ERET, DERET or WAIT, PAUSE. Need to add these to instruction
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// list. TBD.
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)
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break;
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if (delayHasHazard(FI, sawLoad, sawStore, RegDefs, RegUses)) {
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insertDefsUses(FI, RegDefs, RegUses);
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continue;
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}
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Filler = FI;
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return true;
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}
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return false;
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}
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bool Filler::delayHasHazard(MachineBasicBlock::iterator candidate,
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bool &sawLoad, bool &sawStore,
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SmallSet<unsigned, 32> &RegDefs,
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SmallSet<unsigned, 32> &RegUses) {
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if (candidate->isImplicitDef() || candidate->isKill())
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return true;
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// Loads or stores cannot be moved past a store to the delay slot
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// and stores cannot be moved past a load.
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if (candidate->mayLoad()) {
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if (sawStore)
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return true;
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sawLoad = true;
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}
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if (candidate->mayStore()) {
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if (sawStore)
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return true;
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sawStore = true;
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if (sawLoad)
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return true;
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}
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assert((!candidate->isCall() && !candidate->isReturn()) &&
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"Cannot put calls or returns in delay slot.");
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for (unsigned i = 0, e = candidate->getNumOperands(); i!= e; ++i) {
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const MachineOperand &MO = candidate->getOperand(i);
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unsigned Reg;
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if (!MO.isReg() || !(Reg = MO.getReg()))
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continue; // skip
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if (MO.isDef()) {
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// check whether Reg is defined or used before delay slot.
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if (IsRegInSet(RegDefs, Reg) || IsRegInSet(RegUses, Reg))
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return true;
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}
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if (MO.isUse()) {
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// check whether Reg is defined before delay slot.
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if (IsRegInSet(RegDefs, Reg))
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return true;
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}
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}
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return false;
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}
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// Insert Defs and Uses of MI into the sets RegDefs and RegUses.
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void Filler::insertDefsUses(MachineBasicBlock::iterator MI,
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SmallSet<unsigned, 32>& RegDefs,
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SmallSet<unsigned, 32>& RegUses) {
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// If MI is a call or return, just examine the explicit non-variadic operands.
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MCInstrDesc MCID = MI->getDesc();
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unsigned e = MI->isCall() || MI->isReturn() ? MCID.getNumOperands() :
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MI->getNumOperands();
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// Add RA to RegDefs to prevent users of RA from going into delay slot.
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if (MI->isCall())
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RegDefs.insert(Mips::RA);
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for (unsigned i = 0; i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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unsigned Reg;
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if (!MO.isReg() || !(Reg = MO.getReg()))
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continue;
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if (MO.isDef())
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RegDefs.insert(Reg);
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else if (MO.isUse())
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RegUses.insert(Reg);
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}
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}
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//returns true if the Reg or its alias is in the RegSet.
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bool Filler::IsRegInSet(SmallSet<unsigned, 32>& RegSet, unsigned Reg) {
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if (RegSet.count(Reg))
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return true;
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// check Aliased Registers
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for (const uint16_t *Alias = TM.getRegisterInfo()->getAliasSet(Reg);
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*Alias; ++Alias)
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if (RegSet.count(*Alias))
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return true;
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return false;
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}
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