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Pretty print addresses a bit, to not print [%r1+%g0]: just print [%r1] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24813 91177308-0d34-0410-b5e6-96231b3b80d8
476 lines
18 KiB
C++
476 lines
18 KiB
C++
//===-- SparcV8ISelDAGToDAG.cpp - A dag to dag inst selector for SparcV8 --===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by Chris Lattner and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines an instruction selector for the V8 target
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//
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//===----------------------------------------------------------------------===//
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#include "SparcV8.h"
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#include "SparcV8TargetMachine.h"
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#include "llvm/Function.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/CodeGen/SSARegMap.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Support/Debug.h"
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#include <iostream>
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using namespace llvm;
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//===----------------------------------------------------------------------===//
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// TargetLowering Implementation
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//===----------------------------------------------------------------------===//
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namespace V8ISD {
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enum {
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FIRST_NUMBER = ISD::BUILTIN_OP_END+V8::INSTRUCTION_LIST_END,
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CMPICC, // Compare two GPR operands, set icc.
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CMPFCC, // Compare two FP operands, set fcc.
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BRICC, // Branch to dest on icc condition
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BRFCC, // Branch to dest on fcc condition
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Hi, Lo, // Hi/Lo operations, typically on a global address.
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};
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}
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namespace {
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class SparcV8TargetLowering : public TargetLowering {
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public:
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SparcV8TargetLowering(TargetMachine &TM);
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virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
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virtual std::vector<SDOperand>
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LowerArguments(Function &F, SelectionDAG &DAG);
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virtual std::pair<SDOperand, SDOperand>
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LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
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unsigned CC,
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bool isTailCall, SDOperand Callee, ArgListTy &Args,
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SelectionDAG &DAG);
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virtual SDOperand LowerReturnTo(SDOperand Chain, SDOperand Op,
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SelectionDAG &DAG);
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virtual SDOperand LowerVAStart(SDOperand Chain, SDOperand VAListP,
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Value *VAListV, SelectionDAG &DAG);
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virtual std::pair<SDOperand,SDOperand>
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LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
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const Type *ArgTy, SelectionDAG &DAG);
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virtual std::pair<SDOperand, SDOperand>
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LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
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SelectionDAG &DAG);
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};
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}
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SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM)
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: TargetLowering(TM) {
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// Set up the register classes.
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addRegisterClass(MVT::i32, V8::IntRegsRegisterClass);
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addRegisterClass(MVT::f32, V8::FPRegsRegisterClass);
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addRegisterClass(MVT::f64, V8::DFPRegsRegisterClass);
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// Custom legalize GlobalAddress nodes into LO/HI parts.
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setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
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setOperationAction(ISD::ConstantPool , MVT::i32, Custom);
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// Sparc doesn't have sext_inreg, replace them with shl/sra
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
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// Sparc has no REM operation.
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setOperationAction(ISD::UREM, MVT::i32, Expand);
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setOperationAction(ISD::SREM, MVT::i32, Expand);
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// Sparc has no select or setcc: expand to SELECT_CC.
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setOperationAction(ISD::SELECT, MVT::i32, Expand);
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setOperationAction(ISD::SELECT, MVT::f32, Expand);
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setOperationAction(ISD::SELECT, MVT::f64, Expand);
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setOperationAction(ISD::SETCC, MVT::i32, Expand);
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setOperationAction(ISD::SETCC, MVT::f32, Expand);
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setOperationAction(ISD::SETCC, MVT::f64, Expand);
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// Sparc doesn't have BRCOND either, it has BR_CC.
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setOperationAction(ISD::BRCOND, MVT::Other, Expand);
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setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand);
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setOperationAction(ISD::BRTWOWAY_CC, MVT::Other, Expand);
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setOperationAction(ISD::BR_CC, MVT::i32, Custom);
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setOperationAction(ISD::BR_CC, MVT::f32, Custom);
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setOperationAction(ISD::BR_CC, MVT::f64, Custom);
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computeRegisterProperties();
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}
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std::vector<SDOperand>
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SparcV8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
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MachineFunction &MF = DAG.getMachineFunction();
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SSARegMap *RegMap = MF.getSSARegMap();
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std::vector<SDOperand> ArgValues;
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static const unsigned GPR[] = {
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V8::I0, V8::I1, V8::I2, V8::I3, V8::I4, V8::I5
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};
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unsigned ArgNo = 0;
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for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
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MVT::ValueType ObjectVT = getValueType(I->getType());
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assert(ArgNo < 6 && "Only args in regs for now");
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switch (ObjectVT) {
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default: assert(0 && "Unhandled argument type!");
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// TODO: MVT::i64 & FP
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case MVT::i1:
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case MVT::i8:
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case MVT::i16:
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case MVT::i32: {
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unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
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MF.addLiveIn(GPR[ArgNo++], VReg);
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SDOperand Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
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DAG.setRoot(Arg.getValue(1));
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if (ObjectVT != MVT::i32) {
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unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext
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: ISD::AssertZext;
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Arg = DAG.getNode(AssertOp, MVT::i32, Arg,
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DAG.getValueType(ObjectVT));
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Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg);
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}
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ArgValues.push_back(Arg);
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break;
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}
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case MVT::i64: {
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unsigned VRegHi = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
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MF.addLiveIn(GPR[ArgNo++], VRegHi);
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unsigned VRegLo = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
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MF.addLiveIn(GPR[ArgNo++], VRegLo);
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SDOperand ArgLo = DAG.getCopyFromReg(DAG.getRoot(), VRegLo, MVT::i32);
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SDOperand ArgHi = DAG.getCopyFromReg(ArgLo.getValue(1), VRegHi, MVT::i32);
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DAG.setRoot(ArgHi.getValue(1));
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ArgValues.push_back(DAG.getNode(ISD::BUILD_PAIR, MVT::i64, ArgLo, ArgHi));
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break;
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}
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}
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}
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assert(!F.isVarArg() && "Unimp");
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// Finally, inform the code generator which regs we return values in.
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switch (getValueType(F.getReturnType())) {
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default: assert(0 && "Unknown type!");
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case MVT::isVoid: break;
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case MVT::i1:
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case MVT::i8:
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case MVT::i16:
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case MVT::i32:
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MF.addLiveOut(V8::I0);
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break;
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case MVT::i64:
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MF.addLiveOut(V8::I0);
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MF.addLiveOut(V8::I1);
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break;
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case MVT::f32:
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MF.addLiveOut(V8::F0);
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break;
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case MVT::f64:
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MF.addLiveOut(V8::D0);
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break;
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}
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return ArgValues;
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}
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std::pair<SDOperand, SDOperand>
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SparcV8TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
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bool isVarArg, unsigned CC,
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bool isTailCall, SDOperand Callee,
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ArgListTy &Args, SelectionDAG &DAG) {
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assert(0 && "Unimp");
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abort();
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}
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SDOperand SparcV8TargetLowering::LowerReturnTo(SDOperand Chain, SDOperand Op,
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SelectionDAG &DAG) {
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if (Op.getValueType() == MVT::i64) {
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SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op,
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DAG.getConstant(1, MVT::i32));
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SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op,
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DAG.getConstant(0, MVT::i32));
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return DAG.getNode(ISD::RET, MVT::Other, Chain, Lo, Hi);
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} else {
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return DAG.getNode(ISD::RET, MVT::Other, Chain, Op);
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}
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}
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SDOperand SparcV8TargetLowering::
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LowerVAStart(SDOperand Chain, SDOperand VAListP, Value *VAListV,
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SelectionDAG &DAG) {
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assert(0 && "Unimp");
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abort();
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}
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std::pair<SDOperand,SDOperand> SparcV8TargetLowering::
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LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
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const Type *ArgTy, SelectionDAG &DAG) {
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assert(0 && "Unimp");
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abort();
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}
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std::pair<SDOperand, SDOperand> SparcV8TargetLowering::
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LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
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SelectionDAG &DAG) {
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assert(0 && "Unimp");
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abort();
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}
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SDOperand SparcV8TargetLowering::
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LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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switch (Op.getOpcode()) {
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default: assert(0 && "Should not custom lower this!");
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case ISD::BR_CC: {
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SDOperand Chain = Op.getOperand(0);
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SDOperand CC = Op.getOperand(1);
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SDOperand LHS = Op.getOperand(2);
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SDOperand RHS = Op.getOperand(3);
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SDOperand Dest = Op.getOperand(4);
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// Get the condition flag.
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if (LHS.getValueType() == MVT::i32) {
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SDOperand Cond = DAG.getNode(V8ISD::CMPICC, MVT::Flag, LHS, RHS);
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return DAG.getNode(V8ISD::BRICC, MVT::Other, Chain, Dest, CC, Cond);
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} else {
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SDOperand Cond = DAG.getNode(V8ISD::CMPFCC, MVT::Flag, LHS, RHS);
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return DAG.getNode(V8ISD::BRFCC, MVT::Other, Chain, Dest, CC, Cond);
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}
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}
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case ISD::GlobalAddress: {
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GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
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SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
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SDOperand Hi = DAG.getNode(V8ISD::Hi, MVT::i32, GA);
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SDOperand Lo = DAG.getNode(V8ISD::Lo, MVT::i32, GA);
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return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
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}
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case ISD::ConstantPool: {
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Constant *C = cast<ConstantPoolSDNode>(Op)->get();
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SDOperand CP = DAG.getTargetConstantPool(C, MVT::i32);
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SDOperand Hi = DAG.getNode(V8ISD::Hi, MVT::i32, CP);
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SDOperand Lo = DAG.getNode(V8ISD::Lo, MVT::i32, CP);
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return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
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}
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}
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}
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//===----------------------------------------------------------------------===//
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// Instruction Selector Implementation
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//===----------------------------------------------------------------------===//
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//===--------------------------------------------------------------------===//
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/// SparcV8DAGToDAGISel - PPC specific code to select Sparc V8 machine
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/// instructions for SelectionDAG operations.
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///
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namespace {
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class SparcV8DAGToDAGISel : public SelectionDAGISel {
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SparcV8TargetLowering V8Lowering;
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public:
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SparcV8DAGToDAGISel(TargetMachine &TM)
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: SelectionDAGISel(V8Lowering), V8Lowering(TM) {}
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SDOperand Select(SDOperand Op);
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// Complex Pattern Selectors.
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bool SelectADDRrr(SDOperand N, SDOperand &R1, SDOperand &R2);
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bool SelectADDRri(SDOperand N, SDOperand &Base, SDOperand &Offset);
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/// InstructionSelectBasicBlock - This callback is invoked by
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/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
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virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
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virtual const char *getPassName() const {
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return "PowerPC DAG->DAG Pattern Instruction Selection";
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}
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// Include the pieces autogenerated from the target description.
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#include "SparcV8GenDAGISel.inc"
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};
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} // end anonymous namespace
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/// InstructionSelectBasicBlock - This callback is invoked by
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/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
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void SparcV8DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
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DEBUG(BB->dump());
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// Select target instructions for the DAG.
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DAG.setRoot(Select(DAG.getRoot()));
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CodeGenMap.clear();
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DAG.RemoveDeadNodes();
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// Emit machine code to BB.
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ScheduleAndEmitDAG(DAG);
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}
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bool SparcV8DAGToDAGISel::SelectADDRrr(SDOperand Addr, SDOperand &R1,
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SDOperand &R2) {
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if (Addr.getOpcode() == ISD::ADD) {
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if (isa<ConstantSDNode>(Addr.getOperand(1)) &&
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Predicate_simm13(Addr.getOperand(1).Val))
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return false; // Let the reg+imm pattern catch this!
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if (Addr.getOperand(0).getOpcode() == V8ISD::Lo ||
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Addr.getOperand(1).getOpcode() == V8ISD::Lo)
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return false; // Let the reg+imm pattern catch this!
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R1 = Select(Addr.getOperand(0));
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R2 = Select(Addr.getOperand(1));
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return true;
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}
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R1 = Select(Addr);
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R2 = CurDAG->getRegister(V8::G0, MVT::i32);
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return true;
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}
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bool SparcV8DAGToDAGISel::SelectADDRri(SDOperand Addr, SDOperand &Base,
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SDOperand &Offset) {
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if (Addr.getOpcode() == ISD::ADD) {
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
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if (Predicate_simm13(CN)) {
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Base = Select(Addr.getOperand(0));
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Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32);
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return true;
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}
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if (Addr.getOperand(0).getOpcode() == V8ISD::Lo) {
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Base = Select(Addr.getOperand(1));
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Offset = Addr.getOperand(0).getOperand(0);
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return true;
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}
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if (Addr.getOperand(1).getOpcode() == V8ISD::Lo) {
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Base = Select(Addr.getOperand(0));
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Offset = Addr.getOperand(1).getOperand(0);
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return true;
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}
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}
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Base = Select(Addr);
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Offset = CurDAG->getTargetConstant(0, MVT::i32);
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return true;
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}
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SDOperand SparcV8DAGToDAGISel::Select(SDOperand Op) {
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SDNode *N = Op.Val;
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if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
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N->getOpcode() < V8ISD::FIRST_NUMBER)
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return Op; // Already selected.
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// If this has already been converted, use it.
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std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(Op);
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if (CGMI != CodeGenMap.end()) return CGMI->second;
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switch (N->getOpcode()) {
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default: break;
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case ISD::BasicBlock: return CodeGenMap[Op] = Op;
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case V8ISD::CMPICC: {
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// FIXME: Handle compare with immediate.
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SDOperand LHS = Select(N->getOperand(0));
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SDOperand RHS = Select(N->getOperand(1));
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SDOperand Result = CurDAG->getTargetNode(V8::SUBCCrr, MVT::i32, MVT::Flag,
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LHS, RHS);
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return CodeGenMap[Op] = Result.getValue(1);
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}
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case ISD::ADD_PARTS: {
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SDOperand LHSL = Select(N->getOperand(0));
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SDOperand LHSH = Select(N->getOperand(1));
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SDOperand RHSL = Select(N->getOperand(2));
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SDOperand RHSH = Select(N->getOperand(3));
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// FIXME, handle immediate RHS.
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SDOperand Low = CurDAG->getTargetNode(V8::ADDCCrr, MVT::i32, MVT::Flag,
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LHSL, RHSL);
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SDOperand Hi = CurDAG->getTargetNode(V8::ADDXrr, MVT::i32, LHSH, RHSH,
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Low.getValue(1));
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CodeGenMap[SDOperand(N, 0)] = Low;
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CodeGenMap[SDOperand(N, 1)] = Hi;
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return Op.ResNo ? Hi : Low;
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}
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case ISD::SUB_PARTS: {
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SDOperand LHSL = Select(N->getOperand(0));
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SDOperand LHSH = Select(N->getOperand(1));
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SDOperand RHSL = Select(N->getOperand(2));
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SDOperand RHSH = Select(N->getOperand(3));
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// FIXME, handle immediate RHS.
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SDOperand Low = CurDAG->getTargetNode(V8::SUBCCrr, MVT::i32, MVT::Flag,
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LHSL, RHSL);
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SDOperand Hi = CurDAG->getTargetNode(V8::SUBXrr, MVT::i32, LHSH, RHSH,
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Low.getValue(1));
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CodeGenMap[SDOperand(N, 0)] = Low;
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CodeGenMap[SDOperand(N, 1)] = Hi;
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return Op.ResNo ? Hi : Low;
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}
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case ISD::SDIV:
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case ISD::UDIV: {
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// FIXME: should use a custom expander to expose the SRA to the dag.
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SDOperand DivLHS = Select(N->getOperand(0));
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SDOperand DivRHS = Select(N->getOperand(1));
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// Set the Y register to the high-part.
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SDOperand TopPart;
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if (N->getOpcode() == ISD::SDIV) {
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TopPart = CurDAG->getTargetNode(V8::SRAri, MVT::i32, DivLHS,
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CurDAG->getTargetConstant(31, MVT::i32));
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} else {
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TopPart = CurDAG->getRegister(V8::G0, MVT::i32);
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}
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TopPart = CurDAG->getTargetNode(V8::WRYrr, MVT::Flag, TopPart,
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CurDAG->getRegister(V8::G0, MVT::i32));
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// FIXME: Handle div by immediate.
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unsigned Opcode = N->getOpcode() == ISD::SDIV ? V8::SDIVrr : V8::UDIVrr;
|
|
return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS, TopPart);
|
|
}
|
|
case ISD::MULHU:
|
|
case ISD::MULHS: {
|
|
// FIXME: Handle mul by immediate.
|
|
SDOperand MulLHS = Select(N->getOperand(0));
|
|
SDOperand MulRHS = Select(N->getOperand(1));
|
|
unsigned Opcode = N->getOpcode() == ISD::MULHU ? V8::UMULrr : V8::SMULrr;
|
|
SDOperand Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag,
|
|
MulLHS, MulRHS);
|
|
// The high part is in the Y register.
|
|
return CurDAG->SelectNodeTo(N, V8::RDY, MVT::i32, Mul.getValue(1));
|
|
}
|
|
|
|
case ISD::RET: {
|
|
if (N->getNumOperands() == 2) {
|
|
SDOperand Chain = Select(N->getOperand(0)); // Token chain.
|
|
SDOperand Val = Select(N->getOperand(1));
|
|
if (N->getOperand(1).getValueType() == MVT::i32) {
|
|
Chain = CurDAG->getCopyToReg(Chain, V8::I0, Val);
|
|
} else if (N->getOperand(1).getValueType() == MVT::f32) {
|
|
Chain = CurDAG->getCopyToReg(Chain, V8::F0, Val);
|
|
} else {
|
|
assert(N->getOperand(1).getValueType() == MVT::f64);
|
|
Chain = CurDAG->getCopyToReg(Chain, V8::D0, Val);
|
|
}
|
|
return CurDAG->SelectNodeTo(N, V8::RETL, MVT::Other, Chain);
|
|
} else if (N->getNumOperands() > 1) {
|
|
SDOperand Chain = Select(N->getOperand(0)); // Token chain.
|
|
assert(N->getOperand(1).getValueType() == MVT::i32 &&
|
|
N->getOperand(2).getValueType() == MVT::i32 &&
|
|
N->getNumOperands() == 3 && "Unknown two-register ret value!");
|
|
Chain = CurDAG->getCopyToReg(Chain, V8::I1, Select(N->getOperand(1)));
|
|
Chain = CurDAG->getCopyToReg(Chain, V8::I0, Select(N->getOperand(2)));
|
|
return CurDAG->SelectNodeTo(N, V8::RETL, MVT::Other, Chain);
|
|
}
|
|
break; // Generated code handles the void case.
|
|
}
|
|
}
|
|
|
|
return SelectCode(Op);
|
|
}
|
|
|
|
|
|
/// createPPCISelDag - This pass converts a legalized DAG into a
|
|
/// PowerPC-specific DAG, ready for instruction scheduling.
|
|
///
|
|
FunctionPass *llvm::createSparcV8ISelDag(TargetMachine &TM) {
|
|
return new SparcV8DAGToDAGISel(TM);
|
|
}
|